Abstract: A vertically stacked memory device includes a plurality of bit lines extending in a first direction, a plurality of oxide semiconductor layers including a plurality of oxide semiconductor layer sets each including one or more oxide semiconductor layers connected to a separate, respective bit line of the plurality of bit lines and extending in a second direction, the second direction intersecting with the first direction, a plurality of capacitors electrically connected to separate, respective oxide semiconductor layers of the plurality of oxide semiconductor layers, and a plurality of word lines extending to intersect with the plurality of oxide semiconductor layers in a third direction intersecting with both the first direction and the second direction, wherein each oxide semiconductor layer includes an oxide semiconductor material in which a proportion of tin (Sn) among all metals therein is about 50 at % or more to about 100 at % or less.

Abstract: A memory device includes a bit line extending in a first direction, an oxide semiconductor layer extending in a second direction intersecting the first direction and connected to the bit line, the oxide semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region, a capacitor electrically connected to the oxide semiconductor layer, a word line extending to intersect the oxide semiconductor layer in a third direction intersecting the first direction and the second direction, a first insulator on both side surfaces of the source region and the drain region in the third direction, and a second insulator different from the first insulator and on both sides of the channel region in the third direction.

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

Abstract: A layout analysis method includes segmenting a layout pattern into a plurality of polygons in a shape of a rectangle, extracting a conversion characteristic value by applying tolerance to a characteristic value, the characteristic value comprising shape information of each of the plurality of polygons, extracting a total hash value of each of the plurality of polygons by using the conversion characteristic value of each of the plurality of polygons, grouping patterns of the plurality of polygons into a plurality of groups based on the total hash value of each of the plurality of polygons, and extracting a unique pattern from each of the groups.

Abstract: Provided is a ferroelectric thin-film structure including a semiconductor substrate, a first ferroelectric layer on the semiconductor substrate, and a second ferroelectric layer on the semiconductor substrate. The second ferroelectric layer is spaced apart from the first ferroelectric layer and has a different dielectric constant from the first ferroelectric layer. The first ferroelectric layer and the second ferroelectric layer may be different from each other in terms of the amount of a dopant contained therein, and may exhibit different threshold voltages when applied to transistors.

Abstract: Provided is a method for providing augmented content, wherein whether a user terminal is located in a preset unit space is determined on the basis of the location of the user terminal, and if the user terminal is determined to be located in the unit space, an image captured by a camera is displayed through an augmented reality (AR) view by being augmented with content associated with the unit space.

Abstract: A position recognition method and a system based on visual information processing are disclosed A position recognition method according to one embodiment including the steps of: generating a frame image through a camera; transmitting, to a server, a first global pose of the camera and the generated frame image; and receiving, from the server, a second global pose of the camera estimated on the basis of a pose of an object included in the transmitted frame image.

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.

Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.

Abstract: A method of fabricating a semiconductor device includes performing an optical proximity correction (OPC) operation on a layout and forming a photoresist pattern on a substrate using a photomask that is manufactured with the layout corrected by the OPC operation. The OPC operation includes sectioning the layout into a low-level patch and a high-level patch, performing a first OPC operation on the low-level patch, the first OPC operation including generating a first boundary correction pattern of a curvilinear shape on a boundary between the low-level patch and the high-level patch, performing a second OPC operation on the high-level patch, the second OPC operation including a second boundary correction pattern of a curvilinear shape on the boundary, and conforming the first boundary correction pattern and the second boundary correction pattern to each other to generate a conformed boundary correction pattern of a curvilinear shape.

Abstract: Provided are an optical proximity correction (OPC) method capable of maintaining full-chip bias consistency and a mask manufacturing method including the OPC method. The OPC method includes obtaining a first optical proximity corrected (OPCed) design layout by implementing a first OPC on an OPC target design layout; performing a reverse dissection on the OPC target design layout based on the first OPCed design layout to generate first segments; performing a reverse correction to allocate first biases of the first OPCed design layout to the first segments of the OPC target design layout; determining a full-chip representative bias based on a segment grouping of the first segments; applying the full-chip representative bias to an entire chip area; preparing mask data based on the full-chip representative bias that has been applied to the entire chip area; and exposing a mask substrate based on the mask data.

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.

Abstract: A semiconductor device includes an oxide semiconductor layer, a first electrode and a second electrode, which are arranged apart from each other on the oxide semiconductor layer, a metal oxide layer arranged between the oxide semiconductor layer and at least one of the first electrode and the second electrode, and a metal nitride layer arranged between the metal oxide layer and the oxide semiconductor layer.

Abstract: Disclosed are semiconductor fabrication methods and optical proximity correction (OPC) methods. The semiconductor fabrication method comprises performing OPC on a design pattern of a layout to generate a corrected layout, and forming a photoresist pattern on a substrate by using a photomask manufactured with the corrected layout. Performing the OPC includes generating shape points on a contour of the design pattern, producing a hash value of the shape point, selecting a first unique shape point that represents first shape points, determining a first correction bias of the first unique shape point, and creating a correction pattern by applying the first correction bias in common to the first shape points. Producing the hash value includes generating a query range around a target shape point and, based on geometry analysis in the query range, producing the hash value.

Abstract: A ferroelectric structure includes a first polarization enhancement film on a ferroelectric film, wherein the ferroelectric film has a first net polarization in a first direction oriented from the ferroelectric film toward the first polarization enhancement film. The first polarization enhancement film has a second net polarization in a second direction crossing the first direction.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes performing an optical proximity correction (OPC) on a design pattern of a layout and forming a photoresist pattern on a substrate using a photomask manufacture based the corrected layout. The performing of the OPC includes analyzing a cell hierarchy to choose a representative cell in the layout, dividing the design pattern in the representative cell into a plurality of segments including first segments, choosing a first unique segment, which represents the first segments, from the plurality of segments, generating a first correction bias of the first unique segment, applying the first correction bias to all of the first segments to generate a correction pattern, and applying a correction result of the representative cell to other cells that are included in the layout and are of a same type as the representative cell.

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

Abstract: A layout correction method for a semiconductor device includes receiving a design layout including at least a target layer and a reference layer, detecting target edges including target patterns in the target layer, and detecting reference edges including reference patterns in the reference layer, determining a dissection point in a section intersecting a space between reference patterns on a target edge having three or more intersecting reference edges, generating segments by dissecting the target edges based on dissection points set for the target edges, setting an evaluation point at an intermediate point of a section intersecting a reference pattern in a segment intersecting the reference pattern, among the segments, determining a movement amount of segments having evaluation points set on the segments by inputting a feature measured at the evaluation points to a layout correction model, and generating a corrected layout by moving the segments based on the movement amount.