Abstract: A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k-1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

Abstract: A display panel includes a first display region to an N-th display region disposed in a row direction. A P-th display region includes a first pixel circuit including a first pixel driving transistor, a first pixel initialization transistor which receives an initialization voltage, and a first pixel compensation transistor connected in series to the first pixel initialization transistor, where the first pixel compensation transistor connects the first pixel driving transistor and the first pixel initialization transistor to each other based on a compensation gate signal, and a P-th region control circuit including a first control transistor which outputs a high gate voltage of the compensation gate signal, and a second control transistor which outputs a low gate voltage of the compensation gate signal, where the first control transistor and the second control transistor are controlled based on a P-th region control signal.

Abstract: There is provided a display device comprises a substrate; a circuit layer; and an element layer. The element layer comprises light emitting elements disposed in emission areas of a display area of the substrate, and light sensing elements disposed in light sensing areas of the display area. The circuit layer comprises light emitting pixel drivers electrically connected to the light emitting elements; light sensing pixel drivers electrically connected to the light sensing elements; data lines electrically connected to the light emitting pixel drivers; first dummy lines extending in a first direction; second dummy lines extending in parallel with the data lines; and a reset control line electrically connected to the light sensing pixel drivers, extending in the first direction, transmitting a reset control signal for resetting the light sensing pixel drivers, and overlapping at least some of the first dummy lines.

Abstract: A gate signal masking circuit includes a first switching element including a control electrode connected to a masking node, a first electrode connected to a first node and a second electrode connected to a third node, a second switching element including a control electrode connected to a second node, a first electrode receiving a masking signal and a second electrode connected to a fourth node, a third switching element including a control electrode receiving a first signal, a first electrode connected to the fourth node and a second electrode connected to the masking node, a fourth switching element including a control electrode receiving a second signal, a first electrode connected to the masking node and a second electrode connected to a fifth node and a fifth switching element including a control electrode connected to the second node, an electrode connected to the fifth node and another electrode receiving a power.

Abstract: A stage circuit includes: an output unit connected to a first power input terminal and a second power input terminal, the output unit outputting an enable output signal to a first output terminal and an enable carry signal to a second output terminal; a first driver connected to the first power input terminal, the second power input terminal, a clock input terminal, and a second input terminal; and a second driver connected to a first input terminal, the second input terminal, the first power input terminal, and the clock input terminal, the second driver controlling a voltage of the first node. The second driver includes: a first transistor connected between the first node and the clock input terminal, the first transistor including a gate electrode connected to a control node; and a control transistor and a first capacitor, connected in series between the control node and the clock input terminal.

Abstract: According to one or more embodiments of the present disclosure, a clock selection circuit includes an inverter configured to receive an input signal through a first input terminal, and at least one controller configured to receive at least one clock signal and configured to output the clock signal when the input signal is supplied to the inverter.

Abstract: A sub-pixel includes a fourth transistor including a first electrode connected to the third node, a second electrode connected to a second power line, to which a reference voltage is applied, and a gate electrode connected to a first emission control line; a fifth transistor including a first electrode connected to the first node, a second electrode connected to a fourth node, and a gate electrode connected to a second emission control line; a capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light emitting element including a first electrode connected to the fourth node and a second electrode connected to a fourth power line, to which a second driving voltage is applied.

Abstract: A pixel includes a light emitting element including a first electrode, and a second electrode connected to a third power line which transmits a third power voltage, a pulse width modulator which controls an emission time duration of the light emitting element in a frame period based on a data voltage, and a constant current generator which provides a driving current having a constant level to the light emitting element based on a constant current generation voltage applied thereto, where the constant current generator includes a second driving transistor including a gate electrode connected to a third node, a first electrode connected to a second power line which transmits a second power voltage, and a second electrode connected to the first electrode of the light emitting element.

Abstract: A pixel includes a driving switching element including a control electrode connected to a first node, a first electrode connected to a second node and a second electrode connected to a third node, a writing switching element including a control electrode receiving a writing gate signal, a first electrode receiving a data voltage and a second electrode connected to the second node, a compensation switching element including a control electrode receiving a compensation gate signal, a first electrode connected to the first node and a second electrode connected to the third node, a storage capacitor including a first electrode receiving a first power voltage and a second electrode connected to the first node, the light emitting element emitting a light based on a driving current flowing through the driving switching element. The writing gate signal is n-th stage gate signal. The compensation gate signal is (n+k)-th stage gate signal.

Abstract: A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

Abstract: A pixel circuit connects one terminal of a second capacitor to a line of an anode initialization gate signal rather than an anode of a light emitting element such that a change of a gate-source voltage of a first transistor is prevented. The change of the gate-source voltage of the first transistor is prevented, and thus a change of a driving current generated by the first transistor is prevented. Therefore, any damage due to a deterioration of the light emitting element receiving the driving current is prevented, and a luminance accuracy of the light emitting element is preserved.

Abstract: A display device includes a first vertical power line extending in a first direction and receiving a first power source; and a first horizontal power line extending in a second direction intersecting the first direction between a first pixel and a second pixel and receiving the first power source, each of the first pixel and the second pixel includes first to third sub-pixels sequentially disposed in the first direction, the first pixel includes a first common pattern between the first sub-pixel and the second sub-pixel extending in the second direction, the first sub-pixel of the first pixel and the second sub-pixel of the first pixel share the first common pattern and are connected to the first vertical power line, and the third sub-pixel of the first pixel shares the first horizontal power line with the first sub-pixel of the second pixel.

Abstract: There is provided a display device comprises a substrate; a circuit layer; and an element layer. The element layer comprises light emitting elements disposed in emission areas of a display area of the substrate, and light sensing elements disposed in light sensing areas of the display area. The circuit layer comprises light emitting pixel drivers electrically connected to the light emitting elements; light sensing pixel drivers electrically connected to the light sensing elements; data lines electrically connected to the light emitting pixel drivers; first dummy lines extending in a first direction; second dummy lines extending in parallel with the data lines; and a reset control line electrically connected to the light sensing pixel drivers, extending in the first direction, transmitting a reset control signal for resetting the light sensing pixel drivers, and overlapping at least some of the first dummy lines.

Abstract: Disclosed is a display device including a display panel including a plurality of pixels, a plurality of scan lines, and a scan driver. The plurality of pixels includes a first pixel, a second pixel, a third pixel, and a fourth pixel. The plurality of scan lines includes a first scan line, a second scan line, a third scan line, and a fourth scan line. The scan driver includes a plurality of stages that are respectively connected to the plurality of scan lines and outputs a plurality of scan signals. Active periods of scan signals of scan lines adjacent to each other among a plurality of scan lines do not overlap each other.

Abstract: A gate signal masking circuit includes: a connection transistor connecting a first control node and a first transistor based on a connection signal; the first transistor connected to a masking node, the connection transistor and a second control node; a second transistor including a control electrode receiving a carry signal, a first electrode receiving a masking signal and a second electrode connected to a first node; a third transistor including a control electrode receiving an enable signal, a first electrode connected to the first node and a second electrode connected to the masking node; a fourth transistor including a control electrode receiving a second enable signal, a first electrode connected to the masking node and a second electrode connected to a second node; a fifth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node and a second electrode receiving a power voltage.

Abstract: A display device includes a pixel, a sensor including a sensor driving circuit and a sensing element, and a display panel in which a display area is defined. The display area includes a first area and a second area, the sensor driving circuit is connected to the sensing element and includes a reset transistor including a gate electrode that receives a reset control signal, the reset control signal includes a first reset control signal and a second reset control signal different from the first reset control signal, and the first reset control signal is provided to the reset transistor disposed in the first area, and the second reset control signal is provided to the reset transistor disposed in the second area.

Abstract: A light emitting display device includes a unit pixel group including first, second, third, and fourth unit pixels arranged in a 2×2 matrix, and each of the first, second, third, and fourth unit pixel includes a first light emitting region, a second light emitting region, and a third light emitting region that emit lights of three primary colors, respectively, wherein the first, second, and third light emitting regions of the first light emitting region are sequentially in a first diagonal direction, the first, second, third, and fourth light emitting regions of the second unit pixel are sequentially arranged in a second diagonal direction, and the first, second, and third light emitting regions of the third unit pixel are sequentially arranged in a third diagonal direction, and the first, second, and third light emitting regions of the fourth unit pixel are sequentially arranged in a four diagonal direction.

Abstract: A display device includes: a substrate including a display area including emission areas, and a non-display area; a circuit layer on the substrate; and an element layer on the circuit layer, and including light emitting elements corresponding to the emission areas. The circuit layer includes: light emitting pixel drivers electrically connected to the light emitting elements; data lines to transmit data signals; first dummy lines extending in a first direction crossing the data lines; and second dummy lines extending parallel to the data lines, and paired with the data lines, respectively. Each of the data lines and the second dummy lines include an extension portion extending in a second direction crossing the first direction, one data line further includes first protrusions crossing some of the first dummy lines, and one second dummy line paired with the one data line further includes second protrusions crossing others of the first dummy lines.

Abstract: Disclosed is a display device including a display panel including a light emitting element and a pixel circuit connected to the light emitting element, wherein the pixel circuit includes a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second power line, a second transistor connected between the second electrode of the first transistor and a data line to receive a write scan signal, a third transistor connected between the first node and the first electrode of the first transistor to receive a compensation scan signal, a storage capacitor connected between the first node and the second power line, and a fourth transistor connected between the storage capacitor and the second power line to receive a first emission control signal.

Abstract: A display device is disclosed that includes a substrate, first through fourth conductive layers, first through fourth insulating layers, a semiconductor layer, and a light emitting layer. The first conductive layer is disposed on the substrate and includes a first conductive pattern. The first insulating layer is disposed on the first conductive layer. The semiconductor layer is disposed on the first insulating layer and includes a first channel region and a capacitor pattern. The second insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the second insulating layer and includes a first gate electrode overlapping the first channel region. The third insulating layer is disposed on the second conductive layer. The third conductive layer is disposed on the third insulating layer and includes a common electrode. The fourth insulating layer is disposed on the third conductive layer.