Abstract: A method and test system for fast determination of parameter variation statistics provides a mechanism for determining process variation and parameter statistics using low computing power and readily available test equipment. A test array having individually selectable devices is stimulated under computer control to select each of the devices sequentially. A test output from the array provides a current or voltage that dependent on a particular device parameter. The sequential selection of the devices produces a voltage or current waveform, characteristics of which are measured using a digital multi-meter that is interfaced to the computer. The rms value of the current or voltage at the test output is an indication of the standard deviation of the parameter variation and the DC value of the current or voltage is an indication of the mean value of the parameter.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.

Abstract: Calibration of a non-contact current sensor provides improved accuracy for measuring current conducted through a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined DC current is injected through a conductor integrated in the non-contact current sensor. The magnitude of the magnetic field is measured using a sensing element of the non-contact current sensor. Then, when operating in measurement mode, a current conducted in a wire passing through the non-contact current sensor is determined by correcting the output of the non-contact current sensor using the result of the measurement made in the calibration mode.

Abstract: A mechanism is provided for statistical determination of power circuit connectivity based on signal detection in a circuit. Signal data from the circuit gathered and a determination is made as to whether a signal of interest is present in the gathered signal data from the circuit using a statistical analysis of the gathered signal data. The statistical analysis comprises using a mean current value and statistical deviation of the current value of the signal data over a predetermined period of time to compute a confidence range. The confidence range is compared to a first threshold and a second threshold. A determination is made that the signal is present in response to the confidence range being above the first threshold. A determination is made that the signal is not present in response to the confidence range being below the second threshold.

Abstract: A method and test circuit provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

Abstract: A mechanism is provided for rapid estimation of temperature rise in wires due to Joule heating. The mechanism provides fast and accurate estimation of temperature rise in wires due to self heating. Fast estimation is important to handle millions of nets at the full-chip level. The mechanism models lateral heat flow by considering longitudinal heat flow along the wire and lateral thermal coupling to the other wires in the same level. Lateral heat flow can have a significant effect on the temperature rise. The mechanism also models vertical heat flow to the substrate and the heat sink by considering thermal conductivities of vias and inter-layer dielectric (ILD). The mechanism efficiently solves the thermal system to enable physical design optimizations (e.g., wire sizing, etc.) for fixing electromigration violations.

Abstract: According to a method of simulation data processing, a difference is determined between a simulated value of a characteristic for a simulated integrated circuit device and a corresponding empirical value of the characteristic for a fabricated integrated circuit device. A data structure containing a simulation model of the fabricated integrated circuit device is accessed, where the data structure includes a plurality of entries each accessed via a unique index and an index used to access the data structure is offset in accordance with the difference between the simulated value and the empirical value. Operation of the simulated integrated circuit device is then simulated utilizing a value obtained from one of the plurality of entries of the data structure. Results of the simulation are stored in a data storage medium.

Abstract: Calibration of a non-contact current sensor provides improved accuracy for measuring current conducted through a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined DC current is injected through a conductor integrated in the non-contact current sensor. The magnitude of the magnetic field is measured using a sensing element of the non-contact current sensor. Then, when operating in measurement mode, a current conducted in a wire passing through the non-contact current sensor is determined by correcting the output of the non-contact current sensor using the result of the measurement made in the calibration mode.

Abstract: A mechanism is provided for multiple patterning lithography with conflict removal aware coloring. The mechanism makes multiple patterning coloring aware of the conflict removal overhead. The coloring solution explicitly considers ease of conflict removal as one of the coloring objectives. The mechanism pre-computes how much shapes can move in each direction. The mechanism generates a conflict graph where nodes represent shapes in the layout and edges represent conflicts between shapes. The mechanism assigns weights to edges based on available spatial slack between conflicting features. The mechanism then uses the weights to guide multiple patterning coloring. The mechanism prioritizes conflicting features with higher weights to be assigned different colors.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: Calibration of a non-contact current sensor provides improved accuracy for measuring current conducted through a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined current is injected through a voltage sensing conductor integrated in the non-contact current sensor. The magnitude of the magnetic field is measured using a sensing element of the non-contact current sensor. Then, when operating in measurement mode, a current conducted in a wire passing through the non-contact current sensor is determined by correcting the output of the non-contact current sensor using the result of the measurement made in the calibration mode. The voltage sensing conductor is used to provide an indication of the magnitude and/or the phase of the electrostatic potential on the wire. The calibration current may be a DC current, and calibration may be performed while the conductor is carrying an AC current.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: Calibration of a non-contact voltage sensor provides improved accuracy for measuring voltage on a conductor such as an AC branch circuit wire. In a calibration mode, a predetermined voltage is imposed on a first voltage sensing conductor integrated in the non-contact voltage sensor, while a voltage on a second voltage sensing conductor is measured using a circuit of predetermined input impedance. The capacitance between the wire and each of the voltage sensing conductors may be the same, so that in measurement mode, when the first and second voltage sensing conductors are coupled together, the effective series capacitance provided in combination with the predetermined input impedance is four times as great. The results of the voltage measurement made in the calibration mode can thereby be used to adjust subsequent voltage measurements made in measurement mode with the first and second voltage sensing conductors combined in parallel.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A mechanism is provided for optimizing a photolithograph mask. A given target pattern is received. An initial fictitious mask is generated from the given target pattern and an initial value of ?2 is selected where the initial value of ?2 is used to determine a light intensity and a wafer image. The light intensity for each pixel in the initial fictitious mask and the wafer image for each pixel in the initial fictitious mask are then determined. A determination is then made as to whether a convergence has been achieved by comparing the wafer image generated from the fictitious mask to the given target pattern. Responsive to a convergence of the wafer image generated from the fictitious mask to the given target pattern, a final mask is generated to use to transfer an image to a wafer.

Abstract: A mechanism is provided for mask assignment for triple patterning lithography. The mechanism identifies tip-to-tip (TT), tip-to-side (TS), and side-to-side (SS) conflicting parts by design rule dependent projection. The mechanism finds stitch location for TT, TS, and SS conflicts separately. The mechanism colors TT, TS, and SS conflicting parts with mask0/mask1, mask0/mask2, mask1/mask2 coloring cycle with each type colored separately. The mechanism uses existing infrastructure of two-way coloring. As a first objective, the mechanism attempts to minimize conflicts. As a second objective, the mechanism attempts to minimize the number of stitches by assigning the two sides of stitches to the same mask. Once coloring of all conflicting parts is done, the mechanism colors non-conflicting parts to maximize minimum overlap of exposures and to use both colors if two sides are different colors and one color if both sides are the same color.