Abstract: A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.

Abstract: A method and system for determining element voltage selection control values for a storage device provides energy conservation in storage arrays while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. At test time, digital control values are determined for selection circuits for each element that set the virtual power supply rail to the minimum power supply voltage, unless a higher power supply voltage is required for the element to meet performance requirements. The set of digital control values can then be programmed into a fuse or used to adjust a mask at manufacture, or supplied on media along with the storage device and loaded into the device at system initialization.

Abstract: A method and computer program for selecting circuit repairs using redundant elements with consideration of aging effects provides a mechanism for raising short-term and long-term performance of memory arrays beyond present levels/yields. Available redundant elements are used as replacements for selected elements in the array. The elements for replacement are selected by BOL (beginning-of-life) testing at a selected operating point that maximizes the end-of-life (EOL) yield distribution as among a set of operating points at which post-repair yield requirements are met at beginning-of-life (BOL). The selected operating point is therefore the “best” operating point to improve yield at EOL for a desired range of operating points or maximize the EOL operating range. For a given BOL repair operating point, the yield at EOL is computed. The operating point having the best yield at EOL is selected and testing is performed at that operating point to select repairs.

Abstract: An energy efficient storage device using per-element selectable power supply voltages provides energy conservation in storage devices while maintaining a particular performance level. The storage device is partitioned into multiple elements, which may be sub-arrays, rows, columns or individual storage cells. Each element has a corresponding virtual power supply rail that is provided with a selectable power supply voltage. The power supply voltage provided to the virtual power supply rail for an element is set to the minimum power supply voltage unless a higher power supply voltage is required for the element to meet performance requirements. A control cell may be provided within each element that provides a control signal that selects the power supply voltage supplied to the corresponding virtual power supply rail. The state of the cell may be set via a fuse or mask, or values may be loaded into the control cells at initialization of the storage device.

Abstract: A scannable virtual rail ring oscillator circuit and system for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

Abstract: A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient ? relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient ? times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.

Abstract: A test structure for measuring resistances of a large number of interconnect elements such as metal, contacts and vias includes an array of test cells in rows and columns. Power is selectively supplied to test cells in a given column while current is selectively steered from test cells in a given row. A first voltage near the power input node of a device under test (DUT) is selectively sensed, and a second voltage near the current measurement tap is selectively sensed. The resistance of the DUT is the difference of the first and second voltages divided by the current. Additional voltage taps are provided for test cells having multiple resistive elements. This array of test cells can be used to characterize the statistical distribution of resistance variation and to identify physical location of defects in resistive elements.

Abstract: A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.

Abstract: A IC wafer is fabricated using a process of interest to have a plurality of FET devices with different channel lengths (Leff) form a plurality of channel length groups. The threshold voltage (VT) is measured of a statistical sample of the FET devices in each channel length group at two different drain-to-source voltage (VDS). The mean of VT is calculated for each channel length and each VDS. A slope coefficient ? relating VT to Leff is calculated at each VDS. The total variance of VT is calculated at each VDS. Two equations at each VDS, each relating the total variance of VT to the variance of VT with respect to dopant levels and the square of the slope coefficient ? times the variance of Leff, are solved simultaneously to obtain the variance of VT with respect to dopant levels and the variance of Leff.

Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Abstract: A method of measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The characterization array imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: A test system and computer program for measuring threshold voltage variation using a device array provides accurate threshold voltage distribution values for process verification and improvement. The test system and computer program control a characterization array circuit that imposes a fixed drain-source voltage and a constant channel current at individual devices within the array. Another circuit senses the source voltage of the individual device within the array. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: A method for determining threshold voltage variation rapidly provides accurate threshold voltage distribution values for process verification and improvement. The method operates a characterization away including a circuit for imposing a fixed drain-source voltage and a constant channel current at individual devices within the array, while sensing the source voltage of the individual device. The statistical distribution of the threshold voltage is determined directly from the source voltage distribution by offsetting each source voltage by a value determined by completely characterizing one or more devices within the array. The resulting methodology avoids the necessity of otherwise characterizing each device within the array, thus reducing measurement time dramatically.

Abstract: A method and circuits for measuring operating and leakage current of individual blocks within an array of test circuit blocks provides measurement free of error due to leakage currents through non-selected circuit blocks, without requiring an independent test facility for each circuit block. The circuit includes a pair of power supply grids and selection circuits at each test circuit block to select between a test power grid and a “rest” power grid used to supply current to the non-selected circuits. The leakage currents through the non-selected circuits are thus sourced from the rest grid and error that would otherwise be introduced in the test grid current measurement is avoided. The test circuit blocks may be ring oscillators, and the measured current may be the operating and/or leakage current of the ring oscillator. The circuit blocks may also include individual devices for IV (current-voltage) characterization using an additional gate input grid.

Abstract: A system and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

Abstract: A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A test structure for statistical characterization of local device mismatches contains densely populated SRAM devices arranged in a row/column addressable array that enables resource sharing of many devices. The test structure includes a built-in sensing mechanism to calibrate or null out sources of error, and current steering to avoid negative effects of current leakage along spurious paths. The gate and drain lines of each column are driven from both the top and bottom to minimizes parasitic effects. The system can handle a large number of devices while still providing high spatial resolution of current measurements.

Abstract: A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.