Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a layer comprising silicon or amorphous carbon; planarizing the coated backside by a planarizing process; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated backside; and while maintaining the coated backside in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: A method of particle mitigation which includes obtaining a semiconductor wafer having a nonfunctional backside and a functional frontside on which semiconductor devices are formed by one or more lithography processes; coating the backside with a mitigating layer comprising silicon or amorphous carbon; patterning the mitigating layer to form indentations in the mitigating layer; placing the semiconductor wafer onto a wafer chuck such that the wafer chuck makes direct contact with the coated and patterned backside mitigating layer; and while maintaining the coated and patterned backside mitigating layer in direct contact with the wafer chuck, performing a first lithographic process on the frontside.

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.

Abstract: A method comprising steps of removing a first dielectric material, including a hard mask layer and one or more spacer material layers, from a semiconductor device having a sacrificial gate whose sidewalls being covered by said spacer material layers, and a raised source and a raised drain region with both, together with said sacrificial gate, being covered by said hard mask layer, wherein the removing is selective to the sacrificial gate, raised source region and raised drain region and creates a void between each of the raised source region, raised drain region and sacrificial gate. The method includes depositing a conformal layer of a second dielectric material to the semiconductor device, wherein the second material conforms in a uniform layer to the raised source region, raised drain region and sacrificial gate, and fills the void between each of the raised source region, raised drain region and sacrificial gate.

Abstract: A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.

Abstract: A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.

Abstract: A method of making a semiconductor device patterns a first fin in a pFET region, and patterns a second fin in an nFET region. A plurality of conformal microlayers containing a straining material are deposited on the first and second fins. A protective cap material is formed on the first fin, and the conformal layers are selectively removed from the second fin. The straining material is then thermally diffused into the first fin. The protective cap material is removed from the first fin after the thermal annealing and after the conformal micro layers are selectively removed from the second fin.