Abstract: The invention provides methods of treating or preventing malaria comprising administering to an animal an effective amount of a compound of formula I: Q-Y—R1—R2??(I), wherein Q, Y, R1, and R2 are as described herein. Methods of inhibiting a plasmodial surface anion channel of a parasite in an animal are also provided. The invention also provides pharmaceutical compositions comprising a compound represented by formula I in combination with any one or more compounds represented by formulas II, V, and VI. Use of the pharmaceutical compositions for treating or preventing malaria or for inhibiting a plasmodial surface anion channel in animals including humans are also provided. Also provided by the invention are clag3 amino acid sequences and related nucleic acids, vectors, host cells, populations of cells, antibodies, and pharmaceutical compositions.

Abstract: The invention provides methods of treating or preventing malaria comprising administering to an animal an effective amount of a compound of formula (I): Q-Y—R1—R2 (I), wherein Q, Y, R1, and R2 are as described herein. Methods of inhibiting a plasmodial surface anion channel of a parasite in an animal are also provided. The invention also provides pharmaceutical compositions comprising a compound represented by formula (I) in combination with any one or more compounds represented by formulas II, V, and VI. Use of the pharmaceutical compositions for treating or preventing malaria or for inhibiting a plasmodial surface anion channel in animals including humans are also provided. Also provided by the invention are clag3 amino acid sequences and related nucleic acids, vectors, host cells, populations of cells, antibodies, and pharmaceutical compositions.

Abstract: The present invention generally relates to a method for determining the dynamic viscoelastic properties of cells, more particularly to a method for rapidly determining the dynamic viscoelastic properties of healthy and unhealthy cells by determining the phase shift be the application of a modulating force to the cells and the cells' response to the modulating force.

Abstract: Disclosed are inhibitors of the plasmodial surface anion channel (PSAC) inhibitors and the use thereof in treating or preventing malaria in an animal such as a human, comprising administering an effective amount of an inhibitor or a combination of inhibitors. An example of such an inhibitor is a compound of formula I, or a pharmaceutically acceptable salt thereof, wherein R1 to R7 are as described herein.

Abstract: The invention provides methods of treating or preventing malaria comprising administering to an animal an effective amount of a compound of formula (I): Q-Y—R1—R2 (I), wherein Q, Y, R1, and R2 are as described herein. Methods of inhibiting a plasmodial surface anion channel of a parasite in an animal are also provided. The invention also provides pharmaceutical compositions comprising a compound represented by formula (I) in combination with any one or more compounds represented by formulas II, V, and VI. Use of the pharmaceutical compositions for treating or preventing malaria or for inhibiting a plasmodial surface anion channel in animals including humans are also provided. Also provided by the invention are clag3 amino acid sequences and related nucleic acids, vectors, host cells, populations of cells, antibodies, and pharmaceutical compositions.

Abstract: Disclosed are inhibitors of the plasmodial surface anion channel (PSAC) inhibitors and the use thereof in treating or preventing malaria in an animal such as a human, comprising administering an effective amount of an inhibitor or a combination of inhibitors. An example of such an inhibitor is a compound of formula I, Formula (I) or a pharmaceutically acceptable salt thereof, wherein R1 to R7 are as described herein.

Abstract: The present invention relates to an improved process for the preparation of choline salt of fenofibric acid corresponding to formula (I). The present invention also provides crystalline polymorphic form of choline salt of fenofibric acid corresponding to formula (I) designated as form A.

Abstract: Disclosed are inhibitors of the plasmodial surface anion channel (PSAC) inhibitors and the use thereof in treating or preventing malaria in an animal such as a human, comprising administering an effective amount of an inhibitor or a combination of inhibitors. An example of such an inhibitor is a compound of formula I, Formula (I) or a pharmaceutically acceptable salt thereof, wherein R1 to R7 are as described herein.

Abstract: The present invention relates to an improved process for the preparation of tritylated candesartan acid of formula (I) comprising a step of, reacting candesartan acid of formula (II) with trityl chloride in the presence of a base in a ketonic solvent.

Abstract: The power of a signal transmitted from a mobile terminal of a half-duplex TDMA communication system to a base station is controlled by collecting data relating to bit errors in the transmitted signal received on an inbound channel, generating a time-varying statistic of the data. If the time varying statistic indicates that the power should be adjusted, a power control command is embedded in one or more time slots of an outbound channel to the mobile terminal to change the power of the signal. The data may be the bit error rate (BER) reported by a forward error correction decoder and/or returned signal strength information (RSSI). The time varying statistic may be the moving average and standard deviation of the data.

Abstract: A method and system for process model translation is disclosed herein. The method includes generating a common process model based upon a first process model capable of being utilized by a first simulation program. A second process model is then generated based upon the common process model, the second process model being capable of being utilized by a second simulation program.

Abstract: A digital network system accommodates a plurality of network protocols. The digital network system includes a backbone bus for communicating digital information. A first switching interface unit is coupled to the backbone bus and has at least one port connected to a first network. A second switching interface unit is also coupled to the backbone bus and has at least one port connected to a second network. The first and second interface units transferring digital information in first and second network protocols, respectively. First and second memories are coupled to the backbone bus and to the first and second switching interface units, respectively, and store digital information to be transferred between the switching interface units via the backbone bus. The first switching interface unit and the first memory are formed on a single substrate, and the second switching interface unit and the second memory are formed on a single substrate.

Abstract: A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.

Abstract: A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Abstract: A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Abstract: A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.

Abstract: The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Abstract: A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets.

Abstract: A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.