Patents by Inventor Sanjay Havanur
Sanjay Havanur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11824523Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.Type: GrantFiled: December 23, 2021Date of Patent: November 21, 2023Assignee: Vishay-Siliconix, LLCInventors: Sanjay Havanur, M. Ayman Shibib
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Publication number: 20220123740Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.Type: ApplicationFiled: December 23, 2021Publication date: April 21, 2022Inventors: Sanjay Havanur, M. Ayman Shibib
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Patent number: 11218144Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.Type: GrantFiled: September 12, 2019Date of Patent: January 4, 2022Assignee: Vishay-Siliconix, LLCInventors: Sanjay Havanur, M. Ayman Shibib
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Publication number: 20210083660Abstract: Semiconductor device with multiple independent gates. A gate-controlled semiconductor device includes a first plurality of cells of the semiconductor device configured to be controlled by a primary gate, and a second plurality of cells of the semiconductor device configured to be controlled by an auxiliary gate. The primary gate is electrically isolated from the auxiliary gate, and sources and drains of the semiconductor device are electrically coupled in parallel. The first and second pluralities of cells may be substantially identical in structure.Type: ApplicationFiled: September 12, 2019Publication date: March 18, 2021Inventors: Sanjay Havanur, M. Ayman Shibib
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Patent number: 10622994Abstract: A driver for a semiconductor switching device can be configured to step down a supply voltage to generate a first drive voltage. The driver can also generate a second drive voltage equal to the potential difference between the supply voltage and the first drive voltage. The driver can supply the first drive voltage to a control gate of the semiconductor switching device during a first state of a control signal, and a reverse polarity of the second drive voltage during a second state of the control signal.Type: GrantFiled: June 7, 2018Date of Patent: April 14, 2020Assignee: Vishay-Siliconix, LLCInventor: Sanjay Havanur
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Publication number: 20190379375Abstract: A driver for a semiconductor switching device can be configured to step down a supply voltage to generate a first drive voltage. The driver can also generate a second drive voltage equal to the potential difference between the supply voltage and the first drive voltage.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Inventor: Sanjay HAVANUR
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Patent number: 8633512Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: GrantFiled: April 24, 2012Date of Patent: January 21, 2014Assignee: Alpha & Omega Semiconductor, Inc.Inventor: Sanjay Havanur
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Patent number: 8264861Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½Vzx. In another embodiment, a proposed power switching device with integrated VDS clamping includes: In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: GrantFiled: February 25, 2011Date of Patent: September 11, 2012Assignee: Alpha & Omega Semiconductor, Inc.Inventor: Sanjay Havanur
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Publication number: 20120205745Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX +½Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes a switching FET; and a Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: ApplicationFiled: April 24, 2012Publication date: August 16, 2012Inventor: Sanjay Havanur
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Patent number: 8207017Abstract: A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab.Type: GrantFiled: October 29, 2008Date of Patent: June 26, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Sanjay Havanur
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Patent number: 7999600Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes an auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt; an auxiliary FET in parallel with the main switching FET; the auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a predetermined maximum rate of decrease the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain; the auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.Type: GrantFiled: June 5, 2009Date of Patent: August 16, 2011Assignee: Alpha and Omega Semiconductor, Inc.Inventor: Sanjay Havanur
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Publication number: 20110149620Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½Vzx, In another embodiment, a proposed power switching device with integrated VDS-clamping includes: a) A switching FET. b) A Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: ApplicationFiled: February 25, 2011Publication date: June 23, 2011Inventor: Sanjay Havanur
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Patent number: 7898831Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½ Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes: a) A switching FET. b) A Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: GrantFiled: May 9, 2008Date of Patent: March 1, 2011Assignee: Alpha and Omega Semiconductor Inc.Inventor: Sanjay Havanur
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Patent number: 7876584Abstract: A secondary FETsc control circuit is disclosed for controlling FETsc of transformer coupled synchronous rectified flyback converter (TCSC). The control circuit includes source-drain voltage VSD sense trigger with output VSD-trigger activated upon positive 0-crossing of VSD. Drain-source current IDS sense trigger with output IDS-trigger activated upon positive 0-crossing of IDS. Secondary coil voltage Vsec sense trigger with output Vsec-trigger activated upon sensing negative Vsec. A multi-trigger gate driver (MTGD) has trigger inputs coupled to VSD-trigger, IDS-trigger, Vsec-trigger and drive output driving the FETsc gate. The MTGD has logic states of state-I where FETsc is turned off and latched, state-II where FETsc is turned off but unlatched, state-III where FETsc is turned on but unlatched. The MTGD is configured to enter state-III upon VSD-trigger, enter state-I upon IDS-trigger and enter state-IT upon Vsec-trigger.Type: GrantFiled: June 24, 2009Date of Patent: January 25, 2011Assignee: Alpha and Omega Semiconductor IncorporatedInventor: Sanjay Havanur
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Publication number: 20100327947Abstract: A secondary FETsc control circuit is disclosed for controlling FETsc of transformer coupled synchronous rectified flyback converter (TCSC). The control circuit includes source-drain voltage VSD sense trigger with output VSD-trigger activated upon positive 0-crossing of VSD. Drain-source current IDS sense trigger with output IDS-trigger activated upon positive 0-crossing of IDS. Secondary coil voltage Vsec sense trigger with output Vsec-trigger activated upon sensing negative Vsec. A multi-trigger gate driver (MTGD) has trigger inputs coupled to VSD-trigger, IDS-trigger, Vsec-trigger and drive output driving the FETsc gate. The MTGD has logic states of state-I where FETsc is turned off and latched, state-II where FETsc is turned off but unlatched, state-III where FETsc is turned on but unlatched. The MTGD is configured to enter state-III upon VSD-trigger, enter state-I upon IDS-trigger and enter state-IT upon Vsec-trigger.Type: ApplicationFiled: June 24, 2009Publication date: December 30, 2010Inventor: Sanjay Havanur
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Patent number: 7671662Abstract: A semiconductor power device includes a circuit to provide a gate signal wherein the gate signal has a negative temperature coefficient of gate driving voltage for decreasing a gate driving voltage with an increase temperature whereby the semiconductor power device has a net Ids temperature coefficient that is less than or equal to zero. In an exemplary embodiment, the gate voltage driver includes a diode that has a negative forward voltage temperature coefficient connected between a gate and a source of the semiconductor power device. In another embodiment, the gate voltage is integrated with the semiconductor power device manufactured as part of an integrated circuit with the semiconductor power device.Type: GrantFiled: October 28, 2008Date of Patent: March 2, 2010Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Sik K Lui, Anup Bhalla, Sanjay Havanur
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Publication number: 20090279330Abstract: A circuit is proposed for limiting maximum switching FET drain-source voltage (VDS) of a transformer-coupled push pull power converter with maximum DC supply voltage VIN—MAX. Maximum VDS is accentuated by leakage inductances of the push pull transformer and the power converter circuit traces. The limiting circuit bridges the drains of the switching FETs and it includes two serially connected opposing Zener diodes each having a Zener voltage Vzx. The invention is applicable to both N-channel and P-channel FETs. In a specific embodiment, Vzx is selected to be slightly ?2*VIN—MAX with the maximum VDS clamped to about VIN—MAX+½ Vzx. In another embodiment, a proposed power switching device with integrated VDS-clamping includes: a) A switching FET. b) A Zener diode having a first terminal and a second terminal, the second terminal of the Zener diode is connected to the drain terminal of the switching FET.Type: ApplicationFiled: May 9, 2008Publication date: November 12, 2009Inventor: Sanjay Havanur
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Publication number: 20090243715Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.Type: ApplicationFiled: June 5, 2009Publication date: October 1, 2009Inventor: Sanjay Havanur
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Patent number: 7564292Abstract: A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes: An auxiliary inductor in series with the main switching FET for inducing an auxiliary inductive voltage proportional to di/dt. An auxiliary FET in parallel with the main switching FET. The auxiliary FET gate is connected to produce a gate voltage equal to the auxiliary inductive voltage. When the di/dt tends to exceed a pre-determined maximum rate of decrease, the auxiliary FET produces an auxiliary current component counteracting further decrease of the di/dt. The main switching FET and the auxiliary FET can be formed from a single die with shared source and drain. The auxiliary inductor can be implemented as a parasitic inductance of an inherently required bonding wire connecting the main switching FET to its device terminal to simplify packaging with reduced cost.Type: GrantFiled: September 28, 2007Date of Patent: July 21, 2009Assignee: Alpha & Omega Semiconductor, Inc.Inventor: Sanjay Havanur
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Publication number: 20090130799Abstract: A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab.Type: ApplicationFiled: October 29, 2008Publication date: May 21, 2009Inventor: Sanjay Havanur