Patents by Inventor Sanjay K. Yedur
Sanjay K. Yedur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6396059Abstract: A system and method is provided for measuring and determining the resolution of a SEM imaging system employing a crystallographic etched sample with a re-entrant cross-sectional profile. A re-entrant or negative profile is employed because the top-down view seen by the SEM is very sharp due to the fact the edge of the profile has zero width. Therefore, any apparent width seen in the signal is a function of the electron beam width alone. Scanning the beam across the profile provides a signal that moves from a first state to a second state. The time period or sloping portion of the signal from the first state to the second state provides a direct correlation to the electron beam width. Thus, scanning across the sample allows for a calculation of the electron beam width. By scanning across features of different orientations, the shape of the electron beam can be determined. Alternatively, by rotating the electron beam and scanning across the same feature, the shape of the electron beam can be determined.Type: GrantFiled: July 10, 2000Date of Patent: May 28, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bhanwar Singh, Bryan K. Choo, Sanjay K. Yedur
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Patent number: 6376013Abstract: A system and method is provided that facilitates the application of a uniform layer of photoresist material spincoated onto a semiconductor substrate (e.g wafer). The present invention accomplishes this end by utilizing a measurement system that measures the thickness uniformity of the photoresist material applied on a test wafer by a nozzle, and then adjusting the viscosity of the photoresist material by varying the ratio in a solvent/resist mixture, and/or adjusting the temperature of the mixture. A system and method that employs a plurality of nozzles is also provided that disperses resist at different annular regions on a wafer to facilitate the application of a uniform layer of photoresist material spincoated onto the wafer. The system and method utilize a measurement system that measures the thickness and thickness uniformity of each layer of photoresist material applied at each annular region of the wafer.Type: GrantFiled: October 6, 1999Date of Patent: April 23, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Michael K. Templeton
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Patent number: 6373053Abstract: A system is provided for detecting scumming in a wafer. The system includes an analysis system for providing a signal corresponding to a surface portion of the wafer and a processing system operatively coupled to the analysis system. The processing system is configured to determine a shape of at least a portion of the signal and, the processing system detects scumming in the wafer based upon the shape of at least a portion of the signal.Type: GrantFiled: January 31, 2000Date of Patent: April 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Bryan K. Choo, Bhanwar Singh, Sanjay K. Yedur, Khoi A. Phan
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Patent number: 6371134Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.Type: GrantFiled: January 31, 2000Date of Patent: April 16, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo
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Patent number: 6354133Abstract: The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.Type: GrantFiled: December 4, 2000Date of Patent: March 12, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Sanjay K. Yedur, Bhanwar Singh, Bryan K. Choo, Michael K. Templeton, Ramkumar Subramanian
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Patent number: 6326231Abstract: In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 150 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating.Type: GrantFiled: December 8, 1998Date of Patent: December 4, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Bhanwar Singh, Sanjay K. Yedur, Marina V. Plat, Christopher F. Lyons, Bharath Rangarajan, Michael K. Templeton
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Publication number: 20010046791Abstract: In one embodiment, the present invention relates to a method of forming a silicon oxynitride antireflection coating over a metal layer, involving the steps of providing a semiconductor substrate comprising the metal layer over at least part of the semiconductor substrate; depositing a silicon oxynitride layer over the metal layer having a thickness from about 100 Å to about 1500 Å; and forming an oxide layer having a thickness from about 5 Å to about 50 Å over the silicon oxynitride layer to provide the silicon oxynitride antireflection coating.Type: ApplicationFiled: December 8, 1998Publication date: November 29, 2001Inventors: RAMKUMAR SUBRAMANIAN, BHANWAR SINGH, SANJAY K. YEDUR, MARINA V. PLAT, CHRISTOPHER F. LYONS, BHARATH RANGARAJAN, MICHAEL K. TEMPLETON
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Patent number: 6270579Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied.Type: GrantFiled: October 29, 1999Date of Patent: August 7, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
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Publication number: 20010010229Abstract: In one embodiment, the present invention relates to a method of processing a semiconductor structure, involving the steps of providing the semiconductor structure having a patterned resist thereon; stripping the patterned resist from the semiconductor structure, wherein an amount of carbon containing resist debris remain on the semiconductor structure; and contacting the semiconductor structure with ozone thereby reducing the amount of carbon containing resist debris thereon.Type: ApplicationFiled: January 31, 2000Publication date: August 2, 2001Applicant: R. SubramanianInventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Bryan K. Choo
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Patent number: 6248175Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a nozzle adapted to apply a predetermined volume of developer material on a photoresist material layer along a linear path having a length approximately equal to the diameter of the photoresist material layer. A movement system moves the nozzle to a first position offset from a central region of the photoresist material layer for applying a first predetermined volume of developer material to the photoresist material layer while the developer material is spin coated. The movement system also moves the nozzle to a second position offset from the central region for applying a second predetermined volume of developer material to the photoresist material layer while the developer is spin coated. The first position is located on an opposite side of the central region with respect to the second position.Type: GrantFiled: October 29, 1999Date of Patent: June 19, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
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Patent number: 6245493Abstract: A method for creating a roughened surface on a material exposed to light during a photolithographic process is provided. The roughened surface is created on a surface of the material via a plasma etch process. The roughened surface diffuses light incident to the material such that the diffused light causes insubstantial damage to a photoresist subsequently formed on the material.Type: GrantFiled: December 4, 1998Date of Patent: June 12, 2001Inventors: Bhanwar Singh, Bharath Rangarajan, Sanjay K. Yedur, Michael K. Templeton, Christopher F. Lyons
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Patent number: 6197455Abstract: A method of repairing defects in a photomask used in the formation of a semiconductor wafer includes the use of a scanning tunneling microscope. The scanning tunneling microscope includes a very sharp tip having a diameter on the order of 100 Å or less. In order to remove excess material from a mask layer in the photomask, the tip is placed into contact with those regions having such excess material and the tip is used to scrape the excess material away. In order to add material to voids in a mask layer of the photomask, the tip is placed in proximity to those areas in need of the excess material and caused to deposit such material upon, for example, application of a bias voltage to the tip.Type: GrantFiled: January 14, 1999Date of Patent: March 6, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Sanjay K. Yedur, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Kathleen R. Early
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Patent number: 6190062Abstract: One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM.Type: GrantFiled: April 26, 2000Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Bryan K. Choo, Sanjay K. Yedur
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Patent number: 6191046Abstract: A method of reworking a photoresist used to pattern a semiconductor structure is provided. A dielectric layer is formed over an anti-reflective coating, the anti-reflective coating covering a first underlayer, the first underlayer covering a second underlayer. A first photoresist layer is formed and patterened over the dielectric layer to yield a desired photoresist pattern. An undesired feature in the patterned first photoresist layer is determined. The patterned first photoresist layer is removed. A second photoresist layer is formed and patterned over the dielectric layer. Exposed portions of the dielectric layer, the anti-reflective coating and the first underlayer are etched. A thin photoresist layer is formed over exposed portions of the second underlayer. A CMP process is performed to remove the dielectric layer. The thin photoresist layer is stripped.Type: GrantFiled: March 11, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Bhanwar Singh, Sanjay K. Yedur, Bharath Rangarajan
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Patent number: 6187666Abstract: The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.Type: GrantFiled: June 8, 1999Date of Patent: February 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Christopher F. Lyons, Sanjay K. Yedur, Ramkumar Subramanian
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Patent number: 6057914Abstract: The present invention provides a method of detecting a lens aberration in a semiconductor production process, comprising the steps of:forming a feature on a substrate by a process including a step of exposing a radiation-sensitive material to radiation, wherein said radiation passes through a lens;obtaining data relating to a sidewall angle at a plurality of adjacent locations of said feature by scanning at least one surface of said feature with an atomic force microscope;calculating the sidewall angle at said plurality of adjacent locations of said feature based on the data obtained by the atomic force microscope;comparing the sidewall angle obtained from the calculation step to a design sidewall angle for a lens free of aberration, thereby detecting the lens aberration when the comparison reveals a substantial difference between the calculated side wall angle and the design sidewall angle; andidentifying a lens position of the lens aberration by extrapolating from the locations of said feature having said sType: GrantFiled: April 9, 1999Date of Patent: May 2, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Sanjay K. Yedur, Bhanwar Singh, Bharath Rangarajan
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Patent number: 6034771Abstract: A system for regulating heating temperature of a material is provided. The material may be a photoresist, a top or bottom anti-reflective coating, a low K dielectric material, SOG or other spin-on material, for example. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the material. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the material. The measuring system provides material temperature related data to a processor which determines the temperature of the respective portions of the material. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the material and provides for the heating thereof.Type: GrantFiled: November 4, 1998Date of Patent: March 7, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Bharath Rangarajan, Bhanwar Singh, Sanjay K. Yedur, Michael K. Templeton