Abstract: An interconnect structure and methods for making the same include sidewall portions of an interlevel dielectric layer. The sidewall portions have a width less than a minimum feature size for a given lithographic technology and the width is formed by a thickness of the interlevel dielectric layer when conformally formed on vertical surfaces of a mandrel. The sidewall portions form spaced-apart openings. Conductive structures fill the spaced-apart openings and are separated by the sidewall portions to form single damascene structures.

Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

Abstract: A gate dielectric is patterned after formation of a first gate spacer by anisotropic etch of a conformal dielectric layer to minimize overetching into a semiconductor layer. In one embodiment, selective epitaxy is performed to sequentially form raised epitaxial semiconductor portions, a disposable gate spacer, and raised source and drain regions. The disposable gate spacer is removed and ion implantation is performed into exposed portions of the raised epitaxial semiconductor portions to form source and drain extension regions. In another embodiment, ion implantation for source and drain extension formation is performed through the conformal dielectric layer prior to an anisotropic etch that forms the first gate spacer. The presence of the raised epitaxial semiconductor portions or the conformation dielectric layer prevents complete amorphization of the semiconductor material in the source and drain extension regions, thereby enabling regrowth of crystalline source and drain extension regions.

Abstract: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 ?-100 ?) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

Abstract: A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

Abstract: The present invention relates to a branched polyethylene terephthalate-co-isophthalate for use in the manufacture of foamed articles. The branched polyethylene terephthalate-co-isophthalate can be characterized by a composition comprising i) a polyethylene terephthalate-co-isophthalate comprising from about 5 to about 15 weight % of an isophthalic acid, and ii) a branching agent comonomer, wherein the branching agent comonomer is a polyhydric alcohol having functionality of 3 or more and the polyhydric alcohol is present in an amount of from 0.005 to about 0.01 equivalents per mole of total diacids. Other embodiments of the present invention include foamed articles produced from these compositions and processes to produce these compositions and the foamed articles.

Abstract: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 ?-100 ?) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

Abstract: Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.

Abstract: Techniques are discloses to apply an external stress onto the source/drain semiconductor fin sidewall areas and latch the same onto the semiconductor fin before releasing the sidewalls for subsequent salicidation and contact formation. In particular, the present disclosure provides methods in which selected portions of a semiconductor are subjected to an amorphizing ion implantation which disorients the crystal structure of the selected portions of the semiconductor fins, relative to portions of the semiconductor fin that is beneath a gate stack and encapsulated with various liners. At least one stress liner is formed and then stress memorization occurs by performing a stress latching annealing. During this anneal, recrystallization of the disoriented crystal structure occurs. The at least one stress liner is removed and thereafter merging of the semiconductor fins in the source/drain regions is performed.

Abstract: A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 ?-100 ?) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.

Abstract: The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zincsulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition.

Abstract: The invention relates to a design structure, and more particularly, to a design structure for a conductive liner for rad hard total dose immunity and a structure thereof. The structure includes at least one shallow trench isolation structure having oxide material and formed in an SOI. A dielectric liner is formed at an interface of the SOI within the at least one shallow trench isolation structure. A metal or metal alloy layer is formed in the at least one shallow trench isolation structure and between the dielectric liner and the oxide material.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom and/or sidewall of the trench and/or via is usually damaged by a following metallization or cleaning process which may be suitable for dense higher dielectric materials. Embodiments of the present invention may provide a method of repairing process induced dielectric damage from forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes treating an exposed area of the ILD material to create a carbon-rich area, and metallizing the carbon-rich area. One embodiment includes providing treatment to an exposed sidewall area of the ILD material to create a carbon-rich area by irradiating the exposed area using a gas cluster ion beam (GCIB) generated through a gas including a straight chain or branched, aliphatic or aromatic hydrocarbon, and metallizing the carbon-rich area.

Abstract: When an interconnect structure is built on porous ultra low k (ULK) material, the bottom of the trench and/or via is usually damaged by a following metallization process which may be suitable for dense higher dielectric materials. Embodiment of the present invention may provide a method of forming an interconnect structure on an inter-layer dielectric (ILD) material. The method includes steps of treating an exposed area of said ILD material to create a densified area, and metallizing said densified area.

Abstract: The present invention relates to a thermoplastic polymer composition with enhanced gas barrier properties comprising a thermoplastic polymer, an antiplasticizer and a chain extender. Suitable antiplasticizers and suitable chain extenders are disclosed herein. Other embodiments of the present invention include a method to produce such a thermoplastic composition, an article comprising such a thermoplastic composition, and a method for making such an article.

Abstract: The present invention comprises a blend of polyester and a partially aromatic polyamide with an ionic compatibilizer and a cobalt salt. This blend can be processed into a container that has both active and passive oxygen barrier and carbon dioxide barrier properties at an improved color and clarity than containers known in the art. The partially aromatic polyamide is preferably meta-xylylene adipamide. The ionic compatibilizer is preferably 5-sodiumsulfoisophthalic acid or 5-zinesulfoisophthalic acid, or their dialkyl esters such as the dimethyl ester (SIM) and glycol ester (SIPEG). The cobalt salt is selected form the class of cobalt acetate, cobalt carbonate, cobalt chloride, cobalt hydroxide, cobalt naphthenate, cobalt oleate, cobalt linoleate, cobalt octoate, cobalt stearate, cobalt nitrate, cobalt phosphate, cobalt sulfate, cobalt (ethylene glycolate), or mixtures of two or more of these. The partially aromatic polyamide is present in a range from about 1 to about 10 wt. % of said composition.

Abstract: Multi-dimensional surrogation systems and methods are provided that generate at least one data surrogate using information of data and numerous data changes received from at least one data source. The multi-dimensional surrogation transforms data of each data surrogate from a format of the data source to at least one alternative format. Original metadata is extracted from each data surrogate. New metadata is generated by combining portions of the original metadata and components of each data surrogate. The multi-dimensional surrogation generates an extended data surrogate comprising the data surrogate and the new metadata.

Abstract: The invention relates to a method includes etching at least one shallow trench in at least an SIO layer; forming a dielectric liner at an interface of the SIO layer and the SIO layer; forming a metal or metal alloy layer in the shallow trench on the dielectric liner; and filling the shallow trench with oxide material over the metal or metal alloy.

Abstract: Systems and methods are provided for predicting rare events, such as hospitalization events. A set of data records, each containing multiple attributes with one or more values (which may include an “unknown” value), may represent a root node of a decision tree. This root node may be partitioned based on one of the attributes, such that the concentration (e.g., “purity”) of a relevant outcome (e.g., the rare event) is increased in one node and decreased in another. This process may be repeated until a decision tree with sufficiently pure leaf nodes is created. This “purified” decision tree may then be used to predict one or more rare events.

Abstract: Systems and methods are provided for predicting rare events, such as hospitalization events. Data related to health and/or healthcare may be compiled from a number of sources and used to construct a predictive model. The predictive model employ Principal Component Analysis (PCA) and Partial Least Squares (PLS). The data may be arranged in a timeline, and formatted in such a way as to provide discrete temporal “batches”. This arrangement may facilitate the PCA and PLS decomposition of the data into predictive models. These models may then be applied to an individual's data, to create a prediction of healthcare related events.