Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.

Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.

Abstract: Examples may include techniques to implement a SET write operation to a selected memory cell include in a memory array. Examples include selecting the memory cell that includes phase change material and applying various currents over various periods of time during a nucleation stage and a crystal growth stage to cause the memory cell to be in a SET logical state.

Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.

Abstract: Methods, systems, and devices for a modified write voltage for memory devices are described. In an example, the memory device may determine a first set of memory cells to be switched from a first logic state (e.g., a SET state) to a second logic state (e.g., a RESET state) based on a received write command. The memory device may perform a read operation to determine a subset of the first set of memory cells (e.g., a second set of memory cells) having a conductance threshold satisfying a criteria based on a predicted drift of the memory cells. The memory device may apply a RESET pulse to each of the memory cells within the first set of memory cells, where the RESET pulse applied to the second set of memory cells is modified to decrease voltage threshold drift in the RESET state.

Abstract: Multi-level cell (MLC) cross-point memory cells can store more than 1 bit per cell. In one example, MLC write operations for cross-point memory can be achieved by independently changing the state of the switch element and the memory element. The memory cell can be programmed to multiple states, such as a high threshold voltage state (where both the memory element and switch element exhibit a high threshold voltage or resistance), a low threshold voltage state (where both the memory element and select element exhibit a low threshold voltage or resistance), and one or more intermediate resistance states. In one example, additional resistance states can be programmed by setting the switch element and memory element to opposite states (e.g., one of the switch element and memory element is in a high resistance state and the other is in a low resistance state) or by placing both the switch element and memory element in different intermediate states.

Abstract: An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.

Abstract: An apparatus is described. The apparatus includes a cross-point non volatile memory cell array comprised of a first plurality of access lines and a second orthogonal plurality of access lines. Each of the first plurality of access lines are coupled to a first address decoder through a respective pass transistor. The pass transistor is coupled to control circuitry to bias the pass transistor into one of at least two states that include a first active state determined from a second address decoder and a second active state determined from the second address decoder.

Abstract: Techniques for accessing multi-level cell (MLC) crosspoint memory cells are described. In one example, a circuit includes a crosspoint memory cell that can be in one of multiple resistive states (e.g., four or more resistive states). In one example, to perform a read, circuitry coupled with the memory cell applies one or more sub-reads at different read voltages. For example, the circuitry applies a first read voltage and detects if the memory cell thresholds in response to the first read voltage. If the memory cell thresholded in response to the first read voltage, the state of the memory cell can be determined without further reads. If the memory cell did not threshold in response to the first read voltage, a second read voltage with a greater magnitude is applied across the memory cell. If the memory cell thresholded in response to the second read voltage, the state of the memory cell can be determined without further reads.

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.

Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.

Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.

Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.