Patents by Inventor Sanjay Rangan
Sanjay Rangan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190102099Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Applicant: INTEL CORPORATIONInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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Patent number: 10248351Abstract: One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory controller circuitry is to identify an address of a target memory cell to be set. The set pulse determination circuitry is to select a positive polarity set pulse if the target memory cell is included in a positive polarity deck or to select a negative polarity set pulse if the target memory cell is included in a negative polarity deck. Each set pulse includes a respective nucleation portion and a respective growth portion. Each portion has a respective current amplitude and a respective time duration.Type: GrantFiled: September 29, 2017Date of Patent: April 2, 2019Assignee: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan, Enrico Varesi, Innocenzo Tortorelli, Hongmei Wang, Mattia Boniardi
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Publication number: 20190043576Abstract: Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select a current magnitude and a duration of the current magnitude for a programming set pulse based on a polarity of access for the memory cell, a number of prior write cycles for the memory cell, and electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming set pulse to program the memory cell within the array of memory cells. The selected current magnitude and the selected duration of the current magnitude can be applied during the programming set pulse.Type: ApplicationFiled: March 30, 2018Publication date: February 7, 2019Applicant: Intel CorporationInventors: Koushik Banerjee, Lu Liu, Sanjay Rangan
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Patent number: 10185818Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.Type: GrantFiled: February 21, 2017Date of Patent: January 22, 2019Assignee: Intel CorporationInventors: Karthik Sarpatwari, Hongmei Wang, Sanjay Rangan
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Publication number: 20180182456Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: February 12, 2018Publication date: June 28, 2018Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Patent number: 9892785Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: February 24, 2017Date of Patent: February 13, 2018Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20170169886Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: February 24, 2017Publication date: June 15, 2017Inventors: Sanjay RANGAN, Kiran PANGAL, Nevil N. GAJERA, Lu LIU, Gayathri RAO SUBBU
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Publication number: 20170161488Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Applicant: Intel CorporationInventors: Karthik Sarpatwari, Hongmei Wang, Sanjay Rangan
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Patent number: 9608042Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: GrantFiled: February 5, 2016Date of Patent: March 28, 2017Assignee: Intel CorporationInventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Patent number: 9583187Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: GrantFiled: March 28, 2015Date of Patent: February 28, 2017Assignee: Intel CorporationInventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Patent number: 9575727Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.Type: GrantFiled: September 26, 2014Date of Patent: February 21, 2017Assignee: Intel CorporationInventors: Karthik Sarpatwari, Hongmei Wang, Sanjay Rangan
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Publication number: 20160284404Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.Type: ApplicationFiled: March 28, 2015Publication date: September 29, 2016Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
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Publication number: 20160233271Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 5, 2016Publication date: August 11, 2016Inventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Patent number: 9384801Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.Type: GrantFiled: August 15, 2014Date of Patent: July 5, 2016Assignee: INTEL CORPORATIONInventors: Abhinav Pandey, Hanmant P. Belgal, Prashant S. Damle, Arjun Kripanidhi, Sebastian T. Uribe, Dany-Sebastien Ly-Gagnon, Sanjay Rangan, Kiran Pangal
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Publication number: 20160092172Abstract: Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled to circuitry configured to initially set all cells in the array to a high state, send a programming pulse through the array having a current sufficient to randomly set each cell to either the high state or a low state to generate a random distribution of cell states across the array, and to read the random distribution of cell states out of the array.Type: ApplicationFiled: September 26, 2014Publication date: March 31, 2016Inventors: Karthik Sarpatwari, Hongmei Wang, Sanjay Rangan
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Patent number: 9299747Abstract: Embodiments of the present disclosure describe electrode configurations to increase electro-thermal isolation of phase-change memory elements and associated techniques. In an embodiment, an apparatus includes a plurality of phase-change memory (PCM) elements, wherein individual PCM elements of the plurality of PCM elements include a phase-change material layer, a first electrode layer disposed on the phase-change material layer and in direct contact with the phase-change material layer, and a second electrode layer disposed on the first electrode layer and in direct contact with the first electrode layer. Other embodiments may be described and/or claimed.Type: GrantFiled: November 24, 2014Date of Patent: March 29, 2016Assignee: INTEL CORPORATIONInventors: Fabio Pellizzer, Giulio Albini, Stephen W. Russell, Max F. Hineman, Sanjay Rangan
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Publication number: 20160049209Abstract: Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically, in some embodiments memory cells may be configured to store data by being set to a set state or a reset state. In some embodiments, a dummy-read process may be performed on memory cells in the set state prior to a read process. In some embodiments, a modified reset algorithm may be performed on memory cells in the reset state. Other embodiments may be described or claimed.Type: ApplicationFiled: August 15, 2014Publication date: February 18, 2016Inventors: Abhinav PANDEY, Hanmant P. BELGAL, Prashant S. DAMLE, Arjun KRIPANIDHI, Sebastian T. URIBE, Dany-Sebastien LY-GAGNON, Sanjay RANGAN, Kiran PANGAL
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Patent number: 8149680Abstract: Current probe-type memory architecture assumes that the minimum chunk of data that a probe tip can access is one entire track and perhaps only four out of five-thousand, for example, probes participate in the access thereby degrading performance. By subdividing the track into D finer chunks or data zones, D times more probes can cooperate to read out the data, hence increasing the data throughput by Dx. Each tip now only scans approximately one Dth of the track and hence the scan time is reduced by a factor D, while D probes are being utilized in parallel.Type: GrantFiled: December 31, 2009Date of Patent: April 3, 2012Assignee: Intel CorporationInventors: Valluri R. Rao, Sanjay Rangan
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Publication number: 20100226237Abstract: Current probe-type memory architecture assumes that the minimum chunk of data that a probe tip can access is one entire track and perhaps only four out of five-thousand, for example, probes participate in the access thereby degrading performance. By subdividing the track into D finer chunks or data zones, D times more probes can cooperate to read out the data, hence increasing the data throughput by Dx. Each tip now only scans approximately one Dth of the track and hence the scan time is reduced by a factor D, while D probes are being utilized in parallel.Type: ApplicationFiled: December 31, 2009Publication date: September 9, 2010Inventors: Valluri R. Rao, Sanjay Rangan