Abstract: A memory sub-system configured to predictively schedule the transfer of data to reduce idle time and the amount and time of data being buffered in the memory sub-system. For example, write commands received from a host system can be queued without buffering the data of the write commands at the same time. When executing a first write command using a media unit, the memory sub-system can predict a duration to a time the media unit becoming available for execution of a second write command. The communication of the data of the second command from the host system to a local buffer memory of the memory sub-system can be postponed and initiated according to the predicted duration. After the execution of the first write command, the second write command can be executed by the media unit without idling to store the data from the local buffer memory.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A data item is programmed to a first set of management units (MUs) associated with a first portion of one or more memory devices. The first portion includes memory cells of a first type. The first set of MUs is associated with a first physical address. A mapping is generated in a virtual MU data structure that associates the first physical address with a set of virtual MUs associated with the one or more memory devices. An entry associated with the data item is added to a logical-to-physical (L2P) table associated with the one or more memory devices. The entry includes an identifier associated with the set of virtual MUs associated with the one or more memory devices. A detection is made that the data item is programmed to a second set of MUs associated with a second portion of the one or more memory devices. The second portion includes memory cells of a second type. The second set of MUs is associated with a second physical address.

Abstract: A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.

Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

Abstract: Various embodiments described herein provide for extending a size of a memory unit of a memory device, such as a codeword of a page of the memory device, where the memory device can be included by a memory system. In particular, some embodiments implement extending (e.g., increasing) the size of a memory unit (e.g., codeword) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory unit while using a memory unit storage slot (e.g., codeword storage slot in a page) that is smaller in size than the extended memory unit.

Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

Abstract: A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

Abstract: Various embodiments described herein provide for extending a size of a memory unit of a memory device, such as a codeword of a page of the memory device, where the memory device can be included by a memory system. In particular, some embodiments implement extending (e.g., increasing) the size of a memory unit (e.g., codeword) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory unit while using a memory unit storage slot (e.g., codeword storage slot in a page) that is smaller in size than the extended memory unit.

Abstract: Various embodiments described herein provide for extending a size of a memory unit of a memory device, such as a codeword of a page of the memory device, where the memory device can be included by a memory system. In particular, some embodiments implement extending (e.g., increasing) the size of a memory unit (e.g., codeword) to store more data, such as more host data (e.g., user data) and protection data (e.g., parity data), within the memory unit while using a memory unit storage slot (e.g., codeword storage slot in a page) that is smaller in size than the extended memory unit.

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

Abstract: The memory sub-systems of the present disclosure discloses a simulator to simulate a QoS latency model for a just-in-time (JIT) scheduler. In one embodiment, a system receives a workload profile specifying a sequence of memory operations, wherein each memory operation is associated with a type of the memory operation. The system identifies a traffic class associated with each memory operation of the sequence of memory operations. The system queues each memory operation of the sequence of memory operations, based on the traffic class associated with the memory operation, in a scheduling pool of a number of scheduling pools. The system selects, based on a quality of service (QoS) policy, from the scheduling pools, one or more memory operations to be serviced within a scheduling time frame. The system determines, based on a latency profile, latency periods for each memory operation of the one or more memory operations.

Abstract: A memory system identifies, in a logical to physical (L2P) journal associated with a memory device, a first journal entry reflecting a two pass programming operation, where the two pass programming operation includes a first pass to program data to a second memory location identified by a second physical address and a second pass to program a same data to a same second memory location identified by a same second physical address. The system determines whether the second pass of the two pass programming operation is complete. Responsive to determining that the second pass of the two pass programming operation is complete, the system causes a second journal entry of the L2P journal to reference from a first physical address to the second physical address. The system reconstructs the L2P table based on the second journal entry.

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device, which is to perform operations including generating a number of zone map entries for zones of a logical block address (LBA) space that are sequentially mapped to physical address space of the plurality of IC dies, wherein each zone map entry corresponds to a respective data group that has been sequentially written to one or more IC dies; and generating a die identifier and a block identifier for each data block of multiple data blocks of the respective data group, wherein each data block corresponds to a media block of the plurality of IC dies.

Abstract: A method is described, which includes receiving a memory access command that requests access to data in a memory device and determining a location in the memory device for the memory access command. The location for the memory access command indicates a set of managed units in a row of a memory bank of the memory device. The memory access command is fulfilled using the data at the location as a complete response to the memory access command.

Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.

Abstract: Example multi-device storage systems, storage devices, and methods provide hosted services on peer storage devices. Storage devices include a storage medium, a logical mapping memory, and a processor for executing hosted services using the logical mapping memory. Each storage device is configured to communicate with peer storage devices over an interconnect fabric. The logical mapping memory includes storage device media logical mapping information configured in continuous logical blocks with a media block size equal to a page programming size of the storage medium. The logical mapping memory also includes host logical mapping information, configured in host logical blocks with a host block size smaller than the media block size, for the peer storage devices.