Patents by Inventor Sanjay Subbarao

Sanjay Subbarao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220083276
    Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on based on the input/output size identified in the response.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Inventors: Sanjay Subbarao, Mark Ish
  • Patent number: 11269552
    Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: March 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, Steven S. Williams, Mark Ish, John Edward Maroney
  • Patent number: 11249896
    Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 15, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Sanjay Subbarao, Johnny A. Lam, John E. Maroney, Mark Ish
  • Patent number: 11243837
    Abstract: A system and method improve the performance of non-volatile memory storage by rebuilding, on the fly, “lost data” in response to a read request, which identifies data to be read or recovered, by identifying a parity data storage device in a set of data storage devices that contains parity corresponding to the identified data; sending a reconstruction request to a respective data storage device, which may be the parity data storage device or other data storage device in the system, to reconstruct the identified data, and receiving the identified data from the respective data storage device. The reconstruction request commands the respective data storage device to retrieve, via peer-to-peer read requests, from other data storage devices, data from one or more data blocks, and to reconstruct the identified data based on the retrieved data and parity data locally stored at the parity data storage device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Brian W. O'Krafka, Sanjay Subbarao
  • Publication number: 20210407612
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Application
    Filed: September 9, 2021
    Publication date: December 30, 2021
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Patent number: 11204721
    Abstract: A memory sub-system configured to dynamically determine input/output sizes of write commands based on a media physical layout of a memory sub-system. The memory sub-system can identify, dynamically in response to write commands being selected for execution in media units of the memory sub-system, a portion of a media layout that maps from logical addresses identified by the write commands in the logical address space to physical addresses of memory units in the media units. Based on the media layout, an input/output size for a next write command is identified and transmitted to the host system in a response. The host system generates the next write command and configures the amount of data to be written through the next write command based on the input/output size identified in the response.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, Mark Ish
  • Publication number: 20210382658
    Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.
    Type: Application
    Filed: August 3, 2021
    Publication date: December 9, 2021
    Inventors: Sanjay Subbarao, Mark Ish
  • Publication number: 20210373812
    Abstract: A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventor: Sanjay Subbarao
  • Publication number: 20210374060
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Application
    Filed: August 11, 2021
    Publication date: December 2, 2021
    Inventor: Sanjay Subbarao
  • Patent number: 11182091
    Abstract: A method of indirection replay for a flash storage system includes writing data, in a host stream, to blocksets of the flash storage system. The host blocksets are assigned a major sequence number incremented from the most recently closed host blockset. The method includes writing an indirection journal to each host blockset which are associated with the assigned major sequence number. The method includes writing data, in a garbage collection (GC) stream, to other blocksets of the flash storage system. The GC blocksets are assigned a major sequence number, based on the most recently closed host blockset, and a minor sequence number, incremented from the most recently closed GC blockset. The method includes writing an indirection journal to each GC blockset which are associated with the assigned major and minor sequence numbers. The indirection table is constructed by replaying the journals of the blocksets in order of major sequence and minor sequence numbers.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: November 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: David George Dreyer, Colin Christopher McCambridge, Phillip Peterson, Sanjay Subbarao
  • Patent number: 11164652
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Patent number: 11113198
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11113006
    Abstract: A memory sub-system configured to dynamically generate a media layout to avoid media access collisions in concurrent streams. The memory sub-system can identify plurality of media units that are available to write data concurrently, select commands from the plurality of streams for concurrent execution in the available media units, generate and store a portion of a media layout dynamically in response to the commands being selected for concurrent execution in the plurality of media units, and executing the selected commands concurrently by storing data into the memory units according to physical addresses to which logical addresses used in the selected commands are mapped in the dynamically generated portion of the media layout.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11113007
    Abstract: A memory sub-system configured to partially execute write commands from a host system to optimize performance. After receiving a write command from a host system, the memory sub-system can identify, based on a media physical layout, a preferred input/output size for the execution of the write command. The memory sub-system can execute the write command according to the preferred input/output size, configure a response for the write command to identify the second input/output size, and transmit the response identifying the second input/output size to the host system. The host system is configured to generate a subsequent write command to write at least the data that is initially identified in the write command that has been executed but not been included in the execution of the write command performed according to the preferred input/output size.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: September 7, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sanjay Subbarao, Mark Ish
  • Patent number: 11054991
    Abstract: A system and method improve the performance of non-volatile memory storage by automatically, when one or more data storage devices are added to a first set of storage devices in a storage system, resulting in a second set of storage devices, remapping data stored in the first set of storage devices so as to redistribute data across the second set of storage devices while minimizing the amount of data moved to the newly added storage devices. In addition, the remapping and redistribution of data results in empty logical address regions in data storage devices from which data is copied, and a logical address compaction operation is used to remap one or more logical address ranges so as to eliminate the empty logical address regions, without moving data corresponding to the remapped logical address ranges.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: July 6, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Sanjay Subbarao
  • Publication number: 20210191850
    Abstract: A system includes integrated circuit (IC) dies having memory cells and a processing device coupled to the IC dies. The processing device performs operations including storing, within a zone map data structure, zones of a logical block address (LBA) space sequentially mapped to physical address space of the IC dies. A zone map entry in the zone map data structure corresponds to a data group written to one or more of the IC dies. The operations further include storing, within a block set data structure indexed by a block set identifier of the zone map entry, a die identifier and a block identifier for each data block of multiple data blocks of the data group, and writing multiple data groups, which are sequentially mapped across the zones, sequentially across the IC dies. Each data block can correspond to a media (or erase) block of the IC dies.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Sanjay Subbarao, Johnny A. Lam, John E. Maroney, Mark Ish
  • Patent number: 10956071
    Abstract: A Data Storage Device (DSD) includes at least one non-volatile storage media. A command is received to modify a portion of a data object or file, with the command being byte-addressable for overwriting, deleting or adding the modified portion. The modified portion of the data object or file is written with an indication of a page container entry at a storage location in the at least one non-volatile storage media. The page container points to a previous storage location for previously written data for the data object or file that was most recently written before writing the modified portion. A mapping or data container entry in a container data structure is updated for the data object or file to point to the storage location storing the modified portion of the data object or file and the indication of the page container entry.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sanjay Subbarao
  • Publication number: 20200409855
    Abstract: A memory sub-system configured to manage programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system. The memory sub-system counts single-page transitions of atomic programming modes performed within a memory sub-system and determines whether or not to allow any two-page transition of atomic programming modes based on whether an odd or even number of the single-page transitions have been counted. When an odd number of the transitions have been counted, no two-page transition is allowed; otherwise, one or more two-page transitions are allowable. A next transition of atomic programming modes is selected based on the determining of whether or not to allow any two-page transitions.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 31, 2020
    Inventors: Sanjay Subbarao, James Fitzpatrick
  • Patent number: 10878111
    Abstract: Example storage systems, storage devices, and methods provide secure transfer of data between peer storage devices using protection information. Data operation commands may be received that use a protection information data block format for transferring a target data block between peer storage devices. A local data operation may operate on the target data block in a first storage device and compare at least one protection information tag value to a first data check value. At least one destination verification protection information tag value and the target data block may be transferred to a second storage device through a peer communication channel. The destination verification protection information tag value may be compared to a destination data block protection information tag value by the second storage device. The second storage device may then execute a data operation on the target data block.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: December 29, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vladislav Bolkhovitin, Stephen Gold, Adam Roberts, Sanjay Subbarao
  • Publication number: 20200402605
    Abstract: A memory sub-system configured to encode data using an error correcting code and an erasure code for storing data into memory cells and to decode data retrieved from the memory cells. For example, the data units of a predetermined size are separately encoded using the error correcting code (e.g., a low-density parity-check (LDPC) code) to generate parity data of a first layer. Symbols within the data units are cross encoded using the erasure code. Parity symbols of a second layer are calculated according to the erasure code. A collection of parity symbols having a total size equal to the predetermined size can be further encoded using the error correcting code to generate parity data for the parity symbols.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 24, 2020
    Inventors: Sanjay Subbarao, James Fitzpatrick