Patents by Inventor Sanjaysingh Lalbahadoersing

Sanjaysingh Lalbahadoersing has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7453161
    Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: November 18, 2008
    Assignee: ASML Netherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Sanjaysingh Lalbahadoersing, Henry Megens
  • Publication number: 20070284697
    Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.
    Type: Application
    Filed: August 14, 2007
    Publication date: December 13, 2007
    Applicant: ASML Netherlands B.V.
    Inventors: Richard Van Haren, Sanjaysingh Lalbahadoersing, Henry Megens
  • Patent number: 7271073
    Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 18, 2007
    Assignee: ASML Nertherlands B.V.
    Inventors: Richard Johannes Franciscus Van Haren, Sanjaysingh Lalbahadoersing, Henry Megens
  • Publication number: 20070212649
    Abstract: A double patterning system and process using a carbon-based hard mask. The double patterning system provides a means to form hard mask features in single hard mask etch step with a feature spacing smaller than a minimum spacing printable in the hard mask based on a single exposure.
    Type: Application
    Filed: March 7, 2006
    Publication date: September 13, 2007
    Applicant: ASML Netherlands B.V.
    Inventors: Sanjaysingh Lalbahadoersing, Sami Musa
  • Publication number: 20070212648
    Abstract: A double patterning system and process using a carbon-based hard mask. The double patterning system provides a means to form hard mask features in single hard mask etch step with a feature spacing smaller than a minimum spacing printable in the hard mask based on a single exposure.
    Type: Application
    Filed: March 5, 2007
    Publication date: September 13, 2007
    Applicant: ASML Netherlands B.V.
    Inventors: Sanjaysingh Lalbahadoersing, Sami Musa
  • Publication number: 20070212652
    Abstract: A method for alignment mark preservation includes a step of preparing a lower alignment mark structure on a substrate. In one configuration of the invention, the alignment mark structure includes a lower trench. In a further step, a hard mask coating is applied to a substrate that includes the alignment marks. Preferably, the hard mask material is an amorphous carbon material. In a further step, a selected portion of the hard mask located above the lower alignment mark structure is exposed to a dose of radiation. In one aspect of the invention, the surface of regions of the hard mask coating that receive the dose of radiation become elevated with respect to other regions of the hard mask surface. For those elevated regions of the hard mask that are aligned with an underlying alignment mark trench, the elevated regions serve as an alignment mark that preserves the original horizontal position of the underlying alignment mark.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Applicant: ASML Netherlands B.V.
    Inventors: Sanjaysingh Lalbahadoersing, Sami Musa
  • Publication number: 20060003540
    Abstract: A method for manufacturing a marker structure including line elements and trench elements arranged in a repetitive order includes filling the trench elements with silicon dioxide and leveling the marker structure. A sacrificial oxide layer is grown on the semiconductor surface, and a first subset of the line elements is exposed to an ion implantation beam including a dopant species to dope and change an etching rate of the first subset. The substrate is annealed to activate the dopant species, and the semiconductor surface is etched to remove the sacrificial oxide layer and to level the first subset to a first level and to create a topology such that the first subset has a first level differing from a second level of a surface portion of the marker structure different from the first subset .
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Richard Franciscus Van Haren, Sanjaysingh Lalbahadoersing, Henry Megens