Patents by Inventor Sanjive Agarwala
Sanjive Agarwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8904115Abstract: Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.Type: GrantFiled: August 18, 2011Date of Patent: December 2, 2014Assignee: Texas Instruments IncorporatedInventors: Abhijeet Ashok Chachad, Raguram Damodaran, Jonathan (Son) Hung Tran, Timothy David Anderson, Sanjive Agarwala
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Publication number: 20120079204Abstract: Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.Type: ApplicationFiled: August 18, 2011Publication date: March 29, 2012Inventors: Abhijeet Ashok Chachad, Raguram Damodaran, Jonathan (Son) Hung Tran, Timothy David Anderson, Sanjive Agarwala
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Patent number: 7716388Abstract: Command reordering in the hub interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.Type: GrantFiled: May 13, 2005Date of Patent: May 11, 2010Assignee: Texas Instruments IncorporatedInventors: Shoban Srikrishna Jagathesan, Sanjive Agarwala, Kyle Castille, Quang-Dieu An
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Patent number: 7673076Abstract: An enhanced direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.Type: GrantFiled: May 13, 2005Date of Patent: March 2, 2010Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An
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Patent number: 7603487Abstract: A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.Type: GrantFiled: May 13, 2005Date of Patent: October 13, 2009Assignee: Texas Instruments IncorporatedInventors: Shoban Srikrishna Jagathesan, Sanjive Agarwala, Raguram Damodaran
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Patent number: 7577774Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.Type: GrantFiled: May 13, 2005Date of Patent: August 18, 2009Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An, Hung Ong
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Patent number: 7325178Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.Type: GrantFiled: December 3, 2004Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Raguram Damodaran, Timothy D. Anderson, Sanjive Agarwala, Joel J. Graber
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Publication number: 20060259665Abstract: The configurable multiple write-enhanced EDMA of this invention processes multiple priority channels and utilizes as much write data bus as practical. A write queue stores write requests with their corresponding data width and priority. A dispatch circuit dispatches a highest priority maximum data width write request if that is the highest priority stored write request or if the prior dispatch was not a maximum data width write request. The dispatch circuit dispatches two write requests if their total data width is less than or equal to the maximum data width and they both have a priority higher than the highest priority maximum data width write request.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Inventors: Sanjive Agarwala, Kyle Castille, Quang An, David Bell, Natarajan Seshan
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Publication number: 20060256796Abstract: The present invention provides for independent source-read and destination-write functionality for Enhanced Direct Memory Access (EDMA). Allowing source read and destination write pipelines to operate independently makes it possible for the source pipeline to issue multiple read requests and stay ahead of the destination write for fully pipelined operation. The result is that fully pipelined capability may be achieved and utilization of the full DMA bandwidth and maximum throughput performance are provided.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Inventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An, Hung Ong
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Publication number: 20060259569Abstract: A data transfer apparatus with hub and ports includes design configurable hub interface units (HIU) between the ports and corresponding external application units. The configurable HIU provides a single generic superset HIU that can be configured for specific more specialized applications during implementation as part of design synthesis. Configuration allows the super-set configurable HIU to be crafted into any one of several possible special purpose HIUs. This configuration is performed during the design phase and is not applied in field applications. Optimization aimed at eliminating functional blocks not needed in a specific design and simplifying and modifying other functional blocks allows for the efficient configuring of these other types of HIUs. Configuration of HIUs for specific needs can result in significant savings in silicon area and in power consumption.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Inventors: Shoban Jagathesan, Sanjive Agarwala, Raguram Damodaran
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Publication number: 20060259568Abstract: Command reordering in the hub-interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU is to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Inventors: Shoban Jagathesan, Sanjive Agarwala, Kyle Castille, Quang-Dieu An
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Publication number: 20060259648Abstract: An extended direct memory access (EDMA) operation issues a read command to the source port to request data. The port returns the data along with response information, which contains the channel and valid byte count. The EDMA stores the read data into a write buffer and acknowledges to the source port that the EDMA can accept more data. The read response and data can come from more than one port and belong to different channels. Removing channel prioritizing according to this invention allows the EDMA to store read data in the write buffer and the EDMA then can acknowledge the port read response concurrently across all channels. This improves the EDMA inbound and outbound data flow dramatically.Type: ApplicationFiled: May 13, 2005Publication date: November 16, 2006Inventors: Sanjive Agarwala, Kyle Castille, Quang-Dieu An
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Patent number: 7095671Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: GrantFiled: May 3, 2005Date of Patent: August 22, 2006Assignee: Texas Instruments IncorporatedInventors: Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan Le, Sanjive Agarwala
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Patent number: 7047284Abstract: A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.Type: GrantFiled: November 15, 2000Date of Patent: May 16, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, David A. Comisky, Charles L. Fuoco, Iain Robertson, David Hoyle, John Keay, Keith Balmer, Amarjit S. Bhandal, Christopher L. Mobley
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Patent number: 6985982Abstract: In a transfer controller with hub and ports architecture one of the data ports is an active data port. This active data port can supply its own source information, destination information and data quantity in a data transfer request. This data transfer request is serviced in a manner similar to other data transfer requests. The active data port may specify itself as the data destination in an active read. Alternatively, the active data port may specify itself as the data source in an active data write.Type: GrantFiled: October 24, 2001Date of Patent: January 10, 2006Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, David A. Comisky, Charles Fuoco, Raguram Damodaran
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Patent number: 6954468Abstract: The transfer controller with hub and ports uses a write allocation counter and algorithm to control data reads from a source port. The write allocation count is the amount of data that can be consumed immediately by the write reservation station of a slow destination port and the channel data router buffers. This is used to throttle fast source port read operations to whole read bursts until space to adsorb the read data is available. This ensures that the source port response queue is not blocked with data that cannot be consumed by the channel data router and the slow destination port. This condition would otherwise block a fast source port from providing data to the other destination ports.Type: GrantFiled: November 15, 2000Date of Patent: October 11, 2005Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, Iain Robertson, David A. Comisky, Charles L. Fuoco
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Publication number: 20050213411Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: ApplicationFiled: May 3, 2005Publication date: September 29, 2005Inventors: Manjeri Krishnan, Bryan Sheffield, Joel Graber, Duy-Loan Le, Sanjive Agarwala
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Patent number: 6928011Abstract: Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.Type: GrantFiled: July 30, 2003Date of Patent: August 9, 2005Assignee: Texas Instruments IncorporatedInventors: Manjeri Krishnan, Bryan Sheffield, Joel J. Graber, Duy-Loan Le, Sanjive Agarwala
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Publication number: 20050172180Abstract: The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.Type: ApplicationFiled: December 3, 2004Publication date: August 4, 2005Inventors: Raguram Damodaran, Timothy Anderson, Sanjive Agarwala, Joel Graber
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Patent number: 6868087Abstract: A transfer controller with hub and ports is viewed as a communication hub between the various locations of a global memory map. A request queue manager serves as a crucial part of the transfer controller. The request queue manager receives these data transfer request packets from plural transfer requests nodes. The request queue manager sorts transfer request packets by their priority level and stores them in the queue manager memory. The request queue manager processes dispatches transfer request packets to a free data channel based upon priority level and first-in-first-out within priority level.Type: GrantFiled: November 15, 2000Date of Patent: March 15, 2005Assignee: Texas Instruments IncorporatedInventors: Sanjive Agarwala, Iain Robertson, David A. Comisky, Charles L. Fuoco, Christopher L. Mobley