Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.

Abstract: Methods and apparatus to form GaN-based transistors during back-end-of-line processing are disclosed. An example integrated circuit includes a first transistor formed on a first semiconductor substrate. The example integrated circuit includes a dielectric material formed on the first semiconductor substrate. The dielectric material extends over the first transistor. The example integrated circuit further includes a second semiconductor substrate formed on the dielectric material. The example integrated circuit also includes a second transistor formed on the second semiconductor substrate.

Abstract: Techniques are disclosed for forming resonator devices using epitaxially grown piezoelectric films. Given the epitaxy, the films are single crystal or monocrystalline. In some cases, the piezoelectric layer of the resonator device may be an epitaxial III-V layer such as an Aluminum Nitride, Gallium Nitride, or other group III material-nitride (III-N) compound film grown as a part of a single crystal III-V material stack. In an embodiment, the III-V material stack includes, for example, a single crystal AlN layer and a single crystal GaN layer, although any other suitable single crystal piezoelectric materials can be used. An interdigitated transducer (IDT) electrode is provisioned on the piezoelectric layer and defines the operating frequency of the filter. A plurality of the resonator devices can be used to enable filtering specific different frequencies on the same substrate (by varying dimensions of the IDT electrodes).

Abstract: A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10?7? for an area of 1 mm2. Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.

Abstract: Group III-V semiconductor fuses and their methods of fabrication are described. In an example, a fuse includes a gallium nitride layer on a substrate. An oxide layer is disposed in a trench in the gallium nitride layer. A first contact is on the gallium nitride layer on a first side of the trench, the first contact comprising indium, gallium and nitrogen. A second contact is on the gallium nitride layer on a second side of the trench, the second side opposite the first side, the second contact comprising indium, gallium and nitrogen. A filament is over the oxide layer in the trench, the filament coupled to the first contact and to the second contact wherein the filament comprises indium, gallium and nitrogen.

Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.

Abstract: Disclosed herein are integrated circuit (IC) components with dummy structures, as well as related methods and devices. For example, in some embodiments, an IC component may include a dummy structure in a metallization stack. The dummy structure may include a dummy material having a higher Young's modulus than an interlayer dielectric of the metallization stack.

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

Abstract: A semiconductor device includes a silicon pillar disposed on a substrate, the silicon pillar has a sidewall. A group III-N semiconductor material is disposed on the sidewall of the silicon pillar. The group III-N semiconductor material has a sidewall. A doped source structure and a doped drain structure are disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the sidewall of the group III-N semiconductor material between the doped drain structure and the doped source structure. A plurality of portions of gate dielectric layer is disposed on the sidewalls of the group III-N semiconductor material and between the polarization charge inducing layer. A plurality of resistive gate electrodes separated by an interlayer dielectric layer are disposal adjacent to each of the plurality of portions of the gate dielectric layer. A source metal layer is disposed below and in contact with the doped source structure.

Abstract: Methods and apparatus for semiconductor manufacture are disclosed. An example apparatus includes a Gallium Nitride (GaN) substrate; a p-type GaN region positioned on the GaN substrate; a p-type Indium Nitride (InN) region positioned on the GaN substrate and sharing an interface with the p-type GaN region; and a n-type Indium Gallium Nitride (InGaN) region positioned on the GaN substrate and sharing an interface with the p-type InN region.

Abstract: A gate stack structure is disclosed for inhibiting charge leakage in III-V transistor devices. The techniques are particularly well-suited for use in enhancement-mode MOSHEMTs, but can also be used in other transistor designs susceptible to charge spillover and unintended channel formation in the gate stack. In an example embodiment, the techniques are realized in a transistor having a III-N gate stack over a gallium nitride (GaN) channel layer. The gate stack is configured with a relatively thick barrier structure and wide bandgap III-N materials to prevent or otherwise reduce channel charge spillover resulting from tunneling or thermionic processes at high gate voltages. The barrier structure is configured to manage lattice mismatch conditions, so as to provide a robust high performance transistor design. In some cases, the gate stack is used in conjunction with an access region polarization layer to induce two-dimensional electron gas (2DEG) in the channel layer.

Abstract: Techniques are disclosed for producing integrated circuit structures that include one or more geometrically manipulated polarization layers. The disclosed structures can be formed, for instance, using spacer erosion methods in which more than one type of spacer material is deposited on a polarization layer, and the spacer materials and underlying regions of the polarization layer may then be selectively etched in sequence to provide a desired profile shape to the polarization layer. Geometrically manipulated polarization layers as disclosed herein may be formed to be thinner in regions closer to the gate than in other regions, in some embodiments. The disclosed structures may eliminate the need for a field plate and may also be configured with polarization layers that are shorter in lateral length than polarization layers of uniform thickness without sacrificing performance capability. Additionally, the disclosed techniques may provide increased voltage breakdown without sacrificing Ron.

Abstract: Integrated circuit structures configured with low loss transmission lines are disclosed. The structures are implemented with group III-nitride (III-N) semiconductor materials, and are well-suited for use in radio frequency (RF) applications where high frequency signal loss is a concern. The III-N materials are effectively used as a conductive ground shield between a transmission line and the underlying substrate, so as to significantly suppress electromagnetic field penetration at the substrate. In an embodiment, a group III-N polarization layer is provided over a gallium nitride layer, and an n-type doped layer of indium gallium nitride (InzGa1-zN) is provided over or adjacent to the polarization layer, wherein z is in the range of 0.0 to 1.0. In addition to providing transmission line ground shielding in some locations, the III-N materials can also be used to form one or more active and/or passive components (e.g., power amplifier, RF switch, RF filter, RF diode, etc).

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices having multiple resonator thicknesses on a common substrate. A piezoelectric stack is formed in an STI trench and overgrown onto the STI material. In some cases, the piezoelectric stack can include epitaxially grown AlN. In some cases, the piezoelectric stack can include single crystal (epitaxial) AlN in combination with polycrystalline (e.g., sputtered) AlN. The piezoelectric stack thus forms a central portion having a first resonator thickness and end wings extending from the central portion having a different resonator thickness. Each wing may also have different thicknesses. Thus, multiple resonator thicknesses can be achieved on a common substrate, and hence, multiple resonant frequencies on that same substrate. The end wings can have metal electrodes formed thereon, and the central portion can have a plurality of IDT electrodes patterned thereon.

Abstract: Techniques are disclosed herein for ferroelectric-based field-effect transistors (FETs) with threshold voltage (VT) switching for enhanced RF switch transistor on-state and off-state performance. Employing a ferroelectric gate dielectric layer that can switch between two ferroelectric states enables a higher VT during the transistor off-state (VT,hi) and a lower VT during the transistor on-state (VT,lo). Accordingly, the transistor on-state resistance (Ron) can be maintained low due to the available relatively high gate overdrive (Vg,on?VT,lo) while still handling a relatively high maximum RF power in the transistor off-state due to the high VT,hi ?Vg,off value. Thus, the Ron of an RF switch transistor can be improved without sacrificing maximum RF power, and/or vice versa, the maximum RF power can be improved without sacrificing the Ron. A ferroelectric layer (e.g., including HfxZryO) can be formed between a transistor gate dielectric layer and gate electrode to achieve such benefits.

Abstract: Field-effect transistors and methods of manufacturing the same are described herein. An example field-effect transistor includes a substrate, a source above the substrate, a semiconductor region above the source, a drain above semiconductor region, a polarization layer disposed on the semiconductor region between the drain and an end of the semiconductor region, and a gate above the source adjacent the end of the semiconductor region.

Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices using epitaxially grown piezoelectric films. In some cases, the piezoelectric layer of the FBAR may be an epitaxial III-V layer such as an aluminum nitride (AlN) or other group III material-nitride (III-N) compound film grown as a part of a III-V material stack, although any other suitable piezoelectric materials can be used. Use of an epitaxial piezoelectric layer in an FBAR device provides numerous benefits, such as being able to achieve films that are thinner and higher quality compared to sputtered films, for example. The higher quality piezoelectric film results in higher piezoelectric coupling coefficients, which leads to higher Q-factor of RF filters including such FBAR devices. Therefore, the FBAR devices can be included in RF filters to enable filtering high frequencies of greater than 3 GHz, which can be used for 5G wireless standards, for example.

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.