Abstract: Field-effect transistors with buried gates and methods of manufacturing the same are disclosed. An example apparatus includes a source, a drain, and a semiconductor material positioned between the source and the drain. The example apparatus further includes a first gate positioned adjacent the semiconductor material. The example apparatus also includes a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material is positioned between the first and second gates.

Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.

Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.

Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.

Abstract: Embodiments of this disclosure are directed to a multi-gate gallium nitride (GaN) transistor and methods of making the same. The multi-gate GaN transistor includes a gallium nitride layer. The GaN transistor includes two or more gate electrodes between a drain electrode and a source electrode. A polarization layer is located between the first gate electrode and the second gate electrode, the polarization layer forming a two dimensional electron gas (2DEG) within the GaN layer, the 2DEG electrically coupling the first gate electrode and the second gate electrode.

Abstract: A complementary metal oxide semiconductor (CMOS) device that includes a gallium nitride n-type MOS and a silicon P-type MOS is disclosed. The device includes silicon 111 substrate, a gallium nitride transistor formed in a trench in the silicon 111 substrate, the gallium nitride transistor comprising a source electrode, a gate electrode, and a drain electrode. The device further includes a silicon/polysilicon layer formed over the gallium nitride transistor.

Abstract: A P-i-N diode structure includes a group III-N semiconductor material disposed on a substrate. An n-doped raised drain structure is disposed on the group III-N semiconductor material. An intrinsic group III-N semiconductor material is disposed on the n-doped raised drain structure. A p-doped group III-N semiconductor material is disposed on the intrinsic group III-N semiconductor material. A first electrode is connected to the p-doped group III-N semiconductor material. A second electrode is electrically coupled to the n-doped raised drain structure. In an embodiment, a group III-N transistor is electrically coupled to the P-i-N diode. In an embodiment, a group III-N transistor is electrically isolated from the P-i-N diode. In an embodiment, a gate electrode and an n-doped raised drain structure are electrically coupled to the n-doped raised drain structure and the second electrode of the P-i-N diode to form the group III-N transistor.

Abstract: Vertical Group III-N devices and their methods of fabrication are described. In an example, a semiconductor structure includes a doped buffer layer above a substrate, and a group III-nitride (III-N) semiconductor material disposed on the doped buffer layer, the group III-N semiconductor material having a sloped sidewall and a planar uppermost surface. A drain region is disposed adjacent to the doped buffer layer. An insulator layer is disposed on the drain region. A polarization charge inducing layer is disposed on and conformal with the group III-N semiconductor material, the polarization charge inducing layer having a first portion disposed on the sloped sidewall of the group III-N semiconductor material and a second portion disposed on the planar uppermost surface of the group III-N semiconductor material. A gate structure is disposed on the first portion of the polarization charge inducing layer.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for transistors including first and second semiconductor materials between source and drain regions. An example apparatus includes a first semiconductor material and a second semiconductor material adjacent the first semiconductor material. The example apparatus further includes a source proximate the first semiconductor material and spaced apart from the second semiconductor material. The example apparatus also includes a drain proximate the second semiconductor material and spaced apart from the first semiconductor material. The example apparatus includes a gate located between the source and the drain.

Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.

Abstract: Transistor connected diode structures are described. In an example, the transistor connected diode structure includes a group III-N semiconductor material disposed on substrate. A raised source structure and a raised drain structure are disposed on the group III-N semiconductor material. A mobility enhancement layer is disposed on the group III-N semiconductor material. A polarization charge inducing layer is disposed on the mobility enhancement layer, the polarization charge inducing layer having a first portion and a second portion separated by a gap. A gate dielectric layer disposed on the mobility enhancement layer in the gap. A first metal electrode having a first portion disposed on the raised drain structure, a second portion disposed above the second portion of the polarization charge inducing layer and a third portion disposed on the gate dielectric layer in the gap. A second metal electrode disposed on the raised source structure.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure.

Abstract: The present description relates to n-channel gallium nitride transistors which include a recessed gate electrode, wherein the polarization layer between the gate electrode and the gallium nitride layer is less than about 1 nm. In additional embodiments, the n-channel gallium nitride transistors may have an asymmetric configuration, wherein a gate-to drain length is greater than a gate-to-source length. In further embodiment, the n-channel gallium nitride transistors may be utilized in wireless power/charging devices for improved efficiencies, longer transmission distances, and smaller form factors, when compared with wireless power/charging devices using silicon-based transistors.

Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.

Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.

Abstract: Techniques and mechanisms for providing a complementary metal-oxide-semiconductor (CMOS) circuit which includes a group III-nitride (III-N) material. In an embodiment, an n-type transistor of the CMOS circuit comprises structures which are variously disposed on a group III-N semiconductor material. The n-type transistor is coupled to a p-type transistor of the CMOS circuit, wherein a channel region of the p-type transistor comprises a group III-V semiconductor material. The channel region is configured to conduct current along a first direction, where a surface portion of the group III-N semiconductor material extends along a second direction perpendicular to the second direction. In another embodiment, the group III-N semiconductor material includes a gallium-nitride (GaN) compound, and the group III-V semiconductor material includes a nanopillar of an indium antimonide (InSb) compound.

Abstract: Substrate-gated group III-V transistors and associated fabrication methods are described. An example transistor includes a substrate, a gate, and a layer. The gate is located on the substrate. The layer includes a group III material and a group V material. The layer is located on the substrate and the gate. The gate is positioned between the substrate and the layer.