Abstract: A system includes a plurality of nanopore cells. Data corresponding to nanopore states of the plurality of nanopore cells is received. The data is analyzed to determine a compressed output size of the data given at least one compression technique. It is determined whether the compressed output size exceeds a data budget. In the event it is determined that the compressed output size exceeds the data budget, the data is modified. The modified data is outputted.

Abstract: A method of exporting measurements of a nanopore sensor on a nanopore based sequencing chip is disclosed. An electrical characteristic associated with the nanopore sensor is measured. The electrical characteristic associated with the nanopore sensor is processed. A summary for the electrical characteristic and one or more previous electrical characteristics is determined. The summary for the electrical characteristic and the one or more previous electrical characteristics are exported. Determining the summary includes determining that the electrical characteristic and at least a portion of the one or more previous electrical characteristics correspond to a base call event at the nanopore sensor. The summary represents the electrical characteristic and the at least a portion of the one or more previous electrical characteristics.

Abstract: A nanopore measurement circuit is disclosed. The nanopore measurement circuit includes a nanopore electrode, a first analog memory and a second analog memory. The nanopore measurement circuit also includes a switch network that selectively connects the nanopore electrode to at least one of the first analog and the second analog memory.

Abstract: Techniques described herein can apply AC signals with different phases to different groups of nanopore cells in a nanopore sensor chip. When a first group of nanopore cells is in a dark period and is not sampled or minimally sampled by an analog-to-digital converter (ADC) to capture useful data, a second group of nanopore cells is in a bright period during which output signals from the second group of nanopore cells are sampled by the analog-to-digital converter. The reference level setting of the ADC is dynamically changed based on the applied AC signals to fully utilize the dynamic range of the ADC.

Abstract: A system includes a plurality of nanopore cells. Data corresponding to nanopore states of the plurality of nanopore cells is received. The data is analyzed to determine a compressed output size of the data given at least one compression technique. It is determined whether the compressed output size exceeds a data budget. In the event it is determined that the compressed output size exceeds the data budget, the data is modified. The modified data is outputted.

Abstract: A method of exporting measurements of a nanopore sensor on a nanopore based sequencing chip is disclosed. An electrical characteristic associated with the nanopore sensor is measured. The electrical characteristic associated with the nanopore sensor is processed. A summary for the electrical characteristic and one or more previous electrical characteristics is determined. The summary for the electrical characteristic and the one or more previous electrical characteristics are exported. Determining the summary includes determining that the electrical characteristic and at least a portion of the one or more previous electrical characteristics correspond to a base call event at the nanopore sensor. The summary represents the electrical characteristic and the at least a portion of the one or more previous electrical characteristics.

Abstract: Techniques described herein relate to systems and methods for parallel DNA molecules sequencing. A preprocessor can receive raw data frames from a sensor chip including 100,000 or more cells, where each raw data frame can include detection signals from the 100,000 or more cells at a given time during the formation of the 100,000 or more cells or during the DNA molecules sequencing using the 100,000 or more cells. The preprocessor can then extract relevant information for determining states of the cells from the raw data frames, generate one or more digested frames that includes the extracted information, and send the digested frames to a processor for processing, such as base determination. Because the number of digested frames sent to the processor is less than a number of the raw data frames and the digested frames include preprocessed data, the amount of data being transferred to the processor and the amount of data processing by the processor can be reduced.

Abstract: A system includes a plurality of nanopore cells. Data corresponding to nanopore states of the plurality of nanopore cells is received. The data is analyzed to determine a compressed output size of the data given at least one compression technique. It is determined whether the compressed output size exceeds a data budget. In the event it is determined that the compressed output size exceeds the data budget, the data is modified. The modified data is outputted.

Abstract: A nanopore measurement circuit is disclosed. The nanopore measurement circuit includes a nanopore electrode, a first analog memory and a second analog memory. The nanopore measurement circuit also includes a switch network that selectively connects the nanopore electrode to at least one of the first analog and the second analog memory.

Abstract: A system includes a circuit configured to detect a voltage corresponding to an electrical measurement of a nanopore. The system also includes a component configured to compare the voltage to another voltage. Based at least in part on the comparison, a one bit indicator is determined. The one bit indicator indicates whether the voltage indicates a change in a state of the nanopore. In the event it is determined that the voltage indicates the change in the state of the nanopore, a multiple bit signal is provided for output.

Abstract: A method of exporting measurements of a nanopore sensor on a nanopore based sequencing chip is disclosed. An electrical characteristic associated with the nanopore sensor is measured. The electrical characteristic associated with the nanopore sensor is processed. A summary for the electrical characteristic and one or more previous electrical characteristics is determined. The summary for the electrical characteristic and the one or more previous electrical characteristics are exported. Determining the summary includes determining that the electrical characteristic and at least a portion of the one or more previous electrical characteristics correspond to a base call event at the nanopore sensor. The summary represents the electrical characteristic and the at least a portion of the one or more previous electrical characteristics.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A method and apparatus for preventing the overwriting of memory contents during certain scan operations is disclosed. An integrated circuit (IC) may include a memory and a scan chain having a number of serially coupled scan elements. A number of the scan elements may be coupled to circuitry for inputting signals to or receiving signals output from the memory. An inhibit circuit may also be coupled to the circuitry for inputting signals to the memory. During scan shifting operations commensurate with a scan dump mode or a memory dump mode, the inhibit circuit may de-assert one or more control signals that otherwise enable access to the memory in order to prevent shifted data from overwriting the contents stored in the memory. The apparatus may also include a bypass unit coupled to a memory read port, which can be activated to prevent unauthorized access to protected data stored in the memory.

Abstract: An apparatus and method for protecting the contents of a secure register from scan accessibility is disclosed. The secure register may include a number of scannable elements within a scan chain. During a normal scan test mode, the scannable elements of the secure register may be accessibly, as data may be shifted to, from, or through these elements. During certain other modes (e.g., a scan dump or memory dump), a bypass circuit may be invoked to effectively separate the scan elements associated with the secure register from the remainder of the scan chain. During operation in one of these modes, no data may be shifted to, from, or through the scan elements of the secure register. Accordingly, the bypass path may protect secure data stored in the secure register from unauthorized access.

Abstract: Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.

Abstract: Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory controller used to access main memory. The memory controller passes the memory request to a bus interface unit used to access cache memory and a processor. The bus interface unit determines if cache memory can be used to provide the data associated with the PCI client's memory request. While the bus interface unit determines if cache memory may be used, the memory controller continues to process the memory request to main memory. If cache memory can be used, the bus interface unit provides the data to the PCI client and sends a notification to the memory controller.

Abstract: A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible.

Abstract: A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible.