Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Abstract: A half bridge circuit is disclosed. The half bridge circuit includes a low side transistor having a low side transistor gate, where a low side transistor gate voltage at the low side transistor gate is controlled by a low side gate signal. The half bridge circuit also includes a high side transistor having a high side transistor gate, where a high side transistor gate voltage at the high side transistor gate is controlled by a high side gate signal. The half bridge circuit also includes a semiconductor circuit configured to allow current to flow from a ground referenced power supply node to a first floating power supply terminal. The semiconductor circuit includes a first transistor, where a gate voltage is controlled by a gate drive circuit control signal, a source is connected to the ground referenced power supply node, and a drain connected to the first floating power supply terminal.

Abstract: A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.

Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

Abstract: A GaN driver circuit is disclosed. The circuit includes a low side switch causing the voltage at an output node to be a first voltage, a high side switch causing the voltage at the output node to be a second voltage in response to a control signal, and a high side switch driver circuit configured to cause the high side switch to apply the second voltage to the output node. The high side switch driver includes a pull-down switch configured to turn off the high side switch in response to an input signal, and a pass gate configured to cause the high side switch to apply the second voltage to the output node by causing the voltage of the control signal to become substantially equal to the second voltage plus a third voltage.

Abstract: A GaN half bridge circuit is disclosed. The circuit includes a bootstrap power supply voltage generator is configured to supply a first power voltage and includes a switch node. The circuit also includes a bootstrap transistor, a bootstrap transistor drive circuit, and a bootstrap capacitor connected to the switch node and to the bootstrap transistor. The bootstrap capacitor is configured to supply the first power voltage while the voltage at the switch node is equal to the second switch node voltage, the bootstrap transistor is configured to electrically connect the bootstrap capacitor to a power node at a second power voltage while the voltage at the switch node is equal to the first switch node voltage, and the bootstrap power supply voltage generator does not include a separate diode in parallel with the drain and source of the bootstrap transistor.

Abstract: A heterojunction bipolar transistor (HBT) is fabricated using a selectively implanted collector (SIC) implant mask including multiple openings located over the HBT's collector region. During the SIC implant process, resist mask edge (well proximity) effects caused by the SIC dopant passing through the multiple openings generates multiple secondary shallow increased-doping regions in the collector region adjacent to the substrate surface, where the mask openings are sized such that each secondary increased-doping region has a doping concentration that is comparable to primary increased-doping regions, which are simultaneously formed deeper in the SIC region. A base structure and an emitter structure are then formed over the SIC region using known techniques. The secondary increased-doping regions produce enhanced base-collector junction between the SIC region and the base structure that measurably decreases Kirk Effect by way of enhancing the HBT's cutoff frequency (Ft) and break-down voltage (BVCEO).

Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: A GaN half bridge circuit is disclosed. The circuit includes a bootstrap power supply voltage generator is configured to supply a first power voltage and includes a switch node. The circuit also includes a bootstrap transistor, a bootstrap transistor drive circuit, and a bootstrap capacitor connected to the switch node and to the bootstrap transistor. The bootstrap capacitor is configured to supply the first power voltage while the voltage at the switch node is equal to the second switch node voltage, the bootstrap transistor is configured to electrically connect the bootstrap capacitor to a power node at a second power voltage while the voltage at the switch node is equal to the first switch node voltage, and the bootstrap power supply voltage generator does not include a separate diode in parallel with the drain and source of the bootstrap transistor.

Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.

Abstract: A GaN driver circuit is disclosed. The circuit includes a low side switch causing the voltage at an output node to be a first voltage, a high side switch causing the voltage at the output node to be a second voltage in response to a control signal, and a high side switch driver circuit configured to cause the high side switch to apply the second voltage to the output node. The high side switch driver includes a pull-down switch configured to turn off the high side switch in response to an input signal, and a pass gate configured to cause the high side switch to apply the second voltage to the output node by causing the voltage of the control signal to become substantially equal to the second voltage plus a third voltage.

Abstract: A half bridge circuit is disclosed. The circuit includes low side and high side power switches selectively conductive according to one or more control signals. The circuit also includes a low side power switch driver, configured to control the conductivity state of the low side power switch, and a high side power switch driver, configured to control the conductivity state of the high side power switch. The circuit also includes a controller configured to generate the one or more control signals, a high side slew detect circuit configured to prevent the high side power switch driver from causing the high side power switch to be conductive while the voltage at the switch node is increasing, and a low side slew detect circuit configured to prevent the low side power switch driver from causing the low side power switch to be conductive while the voltage at the switch node is decreasing.

Abstract: A half bridge circuit is disclosed. The circuit includes a GaN-based substrate, an oscillator on the substrate, and one or more components forming one or more of a low side power transistor, a low side driver, low side logic circuitry, a high side power transistor, a high side driver, and high side logic circuitry. At least one of the low side power transistor, the low side driver, the low side logic circuitry, the high side power transistor, the high side driver, and the high side logic circuitry is at least partially formed on the substrate. The oscillator is configured to generate non-overlapping pulses, and the non-overlapping pulses are separated by a dead time.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

Abstract: A heterojunction bipolar transistor (HBT) is fabricated using a selectively implanted collector (SIC) implant mask including multiple openings located over the HBT's collector region. During the SIC implant process, resist mask edge (well proximity) effects caused by the SIC dopant passing through the multiple openings generates multiple secondary shallow increased-doping regions in the collector region adjacent to the substrate surface, where the mask openings are sized such that each secondary increased-doping region has a doping concentration that is comparable to primary increased-doping regions, which are simultaneously formed deeper in the SIC region. A base structure and an emitter structure are then formed over the SIC region using known techniques. The secondary increased-doping regions produce enhanced base-collector junction between the SIC region and the base structure that measurably decreases Kirk Effect by way of enhancing the HBT's cutoff frequency (Ft) and break-down voltage (BVCEO).

Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Abstract: A gallium nitride transistor includes a substrate on which a source region, a drain region, a drift region and a gate region are defined. The drift region extends between the source region and the drain region. The gate region includes a combination of enhancement-mode and depletion-mode devices that are positioned across the drift region and are used together to control charge density and mobility of electrons in the drift region with a relatively low threshold voltage (Vth). Enhancement-mode devices are formed using a P-type layer disposed on the substrate and coupled to a gate electrode.

Abstract: A GaN digital circuit is disclosed. The circuit includes a first output node on a substrate, a pull up switch connected to a first output node and a power supply node having a second voltage, a capacitor having a first terminal configured to cause the voltage at the gate of the pull up switch to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage. The circuit also includes a first depletion mode charging switch configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is substantially equal to the second voltage.

Abstract: A half bridge circuit is disclosed. The half bridge circuit includes a low side transistor having a low side transistor gate, where a low side transistor gate voltage at the low side transistor gate is controlled by a low side gate signal. The half bridge circuit also includes a high side transistor having a high side transistor gate, where a high side transistor gate voltage at the high side transistor gate is controlled by a high side gate signal. The half bridge circuit also includes a semiconductor circuit configured to allow current to flow from a ground referenced power supply node to a first floating power supply terminal. The semiconductor circuit includes a first transistor, where a gate voltage is controlled by a gate drive circuit control signal, a source is connected to the ground referenced power supply node, and a drain connected to the first floating power supply terminal.