Patents by Inventor Sarin Deshpande

Sarin Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847711
    Abstract: A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: November 24, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Jon Slaughter, Cong Hai, Hyunwoo Yang, Naganivetha Thiyagarajah, Shukai Ye
  • Patent number: 10777738
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: September 15, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
  • Publication number: 20200287128
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Sarin A. DESHPANDE
  • Publication number: 20200286950
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Kerry Joseph NAGEL, Sanjeev AGGARWAL, Thomas ANDRE, Sarin A. DESHPANDE
  • Publication number: 20200243761
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer. (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: April 10, 2020
    Publication date: July 30, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
  • Patent number: 10700123
    Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Thomas Andre, Sanjeev Aggarwal, Kerry Joseph Nagel, Sarin A. Deshpande
  • Patent number: 10700268
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande
  • Publication number: 20200176672
    Abstract: A magnetoresistive device may include an intermediate region positioned between a magnetically fixed region and a magnetically free region, and spin Hall channel region extending around a sidewall of at least the magnetically free region. An insulator region may extend around a portion of the sidewall such that the insulator region contacts a first portion of the sidewall and the spin Hall channel region contacts a second portion of the sidewall.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Sarin A. DESHPANDE
  • Patent number: 10658576
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 19, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 10600460
    Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: March 24, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin Deshpande, Sanjeev Aggarwal, Jason Janesky, Jon Slaughter, Phillip Lopresti
  • Patent number: 10541362
    Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 21, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
  • Publication number: 20200020852
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Application
    Filed: September 24, 2019
    Publication date: January 16, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Kerry Joseph NAGEL, Chaitanya MUDIVARTHI, Sanjeev AGGARWAL
  • Patent number: 10535390
    Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 14, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Jon Slaughter
  • Publication number: 20200013950
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Sarin A. DESHPANDE, Kerry Joseph NAGEL
  • Patent number: 10483460
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer; depositing a first encapsulation layer on the sidewalls of the second magnetic region and over the dielectric layer; etching the first encapsulation layer which is disposed over the exposed surface of the dielectric layer. The method further includes (a) depositing a second encapsulation layer: (i) on the first encapsulation layer disposed on the sidewalls of the second magnetic region and (ii) over the exposed surface of the dielectric layer and (b) depositing a third encapsulation layer: (i) on the second encapsulation layer which is on the first encapsulation layer and the exposed surface of the dielectric layer. The method also includes etching the remaining layers of the stack/structure (via one or more etch processes).
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: November 19, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Wenchin Lin, Sarin A. Deshpande, Jijun Sun, Sanjeev Aggarwal, Chaitanya Mudivarthi
  • Publication number: 20190334082
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Application
    Filed: July 11, 2019
    Publication date: October 31, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin A. DESHPANDE, Sanjeev AGGARWAL, Kerry Joseph NAGEL
  • Patent number: 10461251
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 29, 2019
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sanjeev Aggarwal, Sarin A. Deshpande, Kerry Joseph Nagel
  • Patent number: 10461250
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: October 29, 2019
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Publication number: 20190280045
    Abstract: A magnetoresistive device may include an annular-shaped magnetic tunnel junction (MTJ) bit having an inner end and an outer end. The MTJ bit may include an annular-shaped magnetically free region and an annular-shaped magnetically fixed region separated by an annular-shaped intermediate layer. A first electrical conductor may be in electrical contact with the inner end of the MTJ bit, and a second electrical conductor may be in electrical contact with the outer end of the MTJ bit.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 12, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kevin Conley, Sarin A. Deshpande
  • Patent number: 10396279
    Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask, after patterning the mask, etching (a) through a first layer of electrically conductive material to form an electrically conductive electrode and (b) through a third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure. The process further includes providing insulating material on or over the sidewalls of the second synthetic antiferromagnetic structure and, thereafter, etching through (a) a second tunnel barrier layer to provide sidewalls thereof, (b) a second layer of ferromagnetic material to provide sidewalls thereof, (c) a first tunnel barrier layer to provide sidewalls thereof, and (d) a first layer of ferromagnetic material to provide sidewalls of the first synthetic antiferromagnetic structure.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: August 27, 2019
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Kerry Joseph Nagel