Patents by Inventor SASANKA ARE

SASANKA ARE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10296457
    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Ruchira Sasanka, Rajat Agarwal
  • Publication number: 20190139646
    Abstract: A decision support tool is provided for predicting uterine contractions. The predicted contractions are determined from measurements of uterine activity (UA). The contraction forecast may be made using a plurality of trained predictive models. The forecasts are formed with linear regressive models based, at least in part, on UA data from a reference population. The predicted contractions may be predictions of contraction duration, contraction peak, and time between contractions. In this way, these predicted contractions may be used for decision support for care plans during labor, such as increased monitoring and/or modifying the care plan.
    Type: Application
    Filed: October 8, 2018
    Publication date: May 9, 2019
    Inventors: ANDREW ROBERTS, SASANKA ARE, JEFFREY W. WALL
  • Publication number: 20190133536
    Abstract: A decision support tool is provided for predicting the neonatal vitality scores of a fetus during delivery, the scores being an indicator of future health for the infant anticipated to be born within a future time interval, measured as time to birth. The predicted neonatal vitality score is determined from measurements of physiological variables monitored during labor, such as uterine activity and fetal heart rate. Fetal heart rate variability and patterns may be detected and computed using the monitored physiological variables, and neonatal vitality scores may be predicted based, at least in part, on the variability metrics and fetal heart rate patterns. Scores may be predicted for different delivery methods, such as vaginal delivery or cesarean delivery, for different time-to-birth intervals. In this way, these scores may be used for decision support for care plans during labor, such as increased monitoring and/or modifying the delivery type.
    Type: Application
    Filed: October 8, 2018
    Publication date: May 9, 2019
    Inventors: ANDREW ROBERTS, SASANKA ARE, JEFFREY W. WALL
  • Publication number: 20190139644
    Abstract: A decision support tool is provided for predicting uterine contractions. The predicted contractions are determined from measurements of uterine activity (UA). The contraction forecast may be made using a plurality of trained predictive models. In one aspect, the forecast is formed with an ensemble of neural network ARIMA models trained using the patient's UA data. Each model within the ensemble may be trained using a different combination of training parameters for the patient's UA data to predict a set of UA measurements for the future time interval. At least some of the sets of UA measurements predicted by the ensemble may be used to form a primary UA forecast for the patient. The predicted contractions may be used for decision support for care plans during labor, such as increased monitoring and/or modifying the care plan.
    Type: Application
    Filed: October 8, 2018
    Publication date: May 9, 2019
    Inventors: ANDREW ROBERTS, SASANKA ARE, JEFFREY W. WALL
  • Publication number: 20190108916
    Abstract: A decision support method and system is provided for monitoring and treating pediatric obesity. Embodiments include generating obesity risk curves corresponding to obesity risk levels, for example, severe and morbid obesity risk levels. Generating obesity risk curves depends on predicting at least one health proxy such as, for example, spend data and chronic conditions. Generating severe obesity curves depends on an age-dependent multiplier. An obesity risk level is assigned to a target pediatric patient using the obesity risk curves dependent on the age-dependent multiplier. In some aspects, an intervening response is initiated based on the assigned obesity risk level.
    Type: Application
    Filed: October 5, 2018
    Publication date: April 11, 2019
    Inventors: ANDREW ROBERTS, SASANKA ARE
  • Publication number: 20190095335
    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Inventor: Ruchira Sasanka
  • Publication number: 20190042225
    Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a nested loop in a set of executable instructions, and determine at runtime if the nested loop is a candidate for cache blocking. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 15, 2018
    Publication date: February 7, 2019
    Applicant: Intel Corporation
    Inventors: Ruchira Sasanka, Karthik Raman, Konstantinos Krommydas
  • Patent number: 10195585
    Abstract: The present disclosure relates to a process for the conversion of biomass to crude bio-oil. Phycocyanin is extracted from the biomass to form phycocyanin extracted biomass (PEB) and subjecting the PEB to HTL conversion to obtain crude bio-oil. PEB results in improved yield of crude bio-oil as compared to the crude bio-oil yield from biomass without first extracting the phycocyanin from the biomass.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: February 5, 2019
    Assignee: Reliance Industries Limited
    Inventors: Badrish Ranjitlal Soni, Mandan Chidambaram, Kshudiram Mantri, Vijayakumar Vinodhkumar, Sasanka Raha, Venkatesh Prasad, Ramesh Bhujade, Santanu Dasgupta, Nagesh Sharma, Raksh Vir Jasra
  • Publication number: 20190035502
    Abstract: Methods and systems for managing care team assignment's for individuals, such as a patient, are provided. Embodiments include receiving indicators of actions that are initiated by a clinician and associated with a patient's care. Using times associated with each action, a time series indicating contribution levels for each clinician may be constructed. Care contribution curves measuring a clinician's care contribution level over time may be generated using the time series and a rate of decay for each action, which may be based on the type of action and the role of the clinician who initiated the action. A care contribution score for each clinician may be determined from the clinician's care contribution curve, and a care team assignment for the patient may be created based on care contribution scores for each clinician who initiated an action.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 31, 2019
    Inventors: ANDREW ROBERTS, SASANKA ARE, JANAE NELSON, BRYCE SCHAFFTER
  • Patent number: 10187251
    Abstract: Disclosed are various embodiments for event processing architecture for real-time user engagement. Events that describe user interactions with client applications are analyzed in real-time when received in a data stream. The events are compared to patterns specified, for example, by administrators. If a pattern is matched based on a comparison to events received in the data stream, a predetermined action may be performed. The processing of events may be performed by a compute engine, which may include a virtual machine or a thread implemented in a parallel computing arrangement.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 22, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Raghunathan Kothandaraman, Mark Aran Aiken, Sasanka Rajaram, Deep Dixit, Gaurav Gupta, Ankit Kumar, Dhaval Parmar
  • Patent number: 10162758
    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: December 25, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Patent number: 10152421
    Abstract: In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka
  • Publication number: 20180333106
    Abstract: Methods and systems for predicting deterioration of a patient's condition within a future time interval based on a time series of values for monitored physiological variables measured from a patient, and in some instances, providing advanced notice to clinicians or caregivers when deterioration is forecasted or modifying treatment for the patient are provided. In particular, deterioration of a patient's condition is based on a Hopf bifurcation model and is predicted using a ratio of deviations for monitored physiological variables. A ratio of deviations relates the standard deviation and root mean square of successive differences for a set of physiological values measured over time. The RoD for one or more variables, such as heart rate, respiratory rate, and blood pressure, may be used to predict the likelihood of the patient's condition deteriorating into an unstable state as what occurs in a Hopf bifurcation.
    Type: Application
    Filed: May 18, 2018
    Publication date: November 22, 2018
    Inventors: ANDREW ROBERTS, SASANKA ARE, DOUGLAS S. McNAIR
  • Publication number: 20180285267
    Abstract: A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Ruchira Sasanka, Rajat Agarwal
  • Patent number: 10038757
    Abstract: Methods and systems are provided for generating personalized greetings for presentation by a personal digital assistant on a client device. An indication is received from the client device associated with the user that the personal digital assistant has been launched on the client device. User-specific information and contextual information is retrieved by querying a user profile database and one or more services. A personalized greeting engine utilizes the user-specific information, such as user inferences and interests, and the contextual information to generate the personalized greetings for presentation by the digital assistant on the client device.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 31, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Sasanka Madiraju, Ayman Farouq Mohammad Almadhoun, Nirav Ashwin Kamdar, Talon Edward Ireland, Melissa Nicole Lim, Ravikiran Arun Aranke, Catherine Lynn Maritan, Tudor Buzasu Klein
  • Publication number: 20180189040
    Abstract: Techniques are disclosed to identify a frequently-executed region of code during runtime execution of the code, generate initial profiling code for the frequently-executed region of code, cause the initial profiling code to be executed for a minimum number of processing cycles of the computer, and identify replacement candidate store instruction(s) that store a value that is not read by the frequently-executed region of code during execution of the initial profiling code. Replacement candidate load instruction(s) may also be identified that load a value that is not stored or loaded by the frequently-executed region of code during execution of the initial profiling code. Optimized code for the frequently-executed region of code may be generated by replacing each of the replacement candidate store or load instructions(s) with a non-temporal store or load instruction. The optimized code may be executed instead of the frequently-executed region of code during subsequent runtime execution.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Inventor: Ruchira Sasanka
  • Publication number: 20180173854
    Abstract: Methods, systems, and computer-readable media for a system and method are provided for assessing the value of predictive models monitoring medical conditions. Trends in an individual's medical condition are determined based on monitoring values, and the trends are associated with the actions performed in response to the monitoring values and in accordance with the predictive models. The trends may indicate that an individual's condition is improving, worsening, or remaining stable in response to the action taken. Models used for multiple conditions for an individual or for a population of individuals may be assessed in this manner to generate knowledge regarding the performance of the models based on the actions taken. This knowledge may be used to assess the value of the models in terms of the models' performance and may provide insight on way to improve the models.
    Type: Application
    Filed: December 21, 2016
    Publication date: June 21, 2018
    Inventors: KANAKASABHA KAILASAM, SASANKA ARE
  • Publication number: 20180165205
    Abstract: A processor includes a processor core and a cache controller coupled to the processor core. The cache controller is to allocate, for a memory, a plurality of cache entries in a cache, wherein the processor core is to: detect an amount of the memory installed in a computing system and, responsive to detecting less than a maximum allowable amount of the memory for the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.
    Type: Application
    Filed: December 9, 2016
    Publication date: June 14, 2018
    Inventor: Ruchira Sasanka
  • Publication number: 20180060049
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
  • Patent number: 9904555
    Abstract: Described herein are mechanisms for continuous automatic tuning of code regions for optimal hardware configurations for the code regions. One mechanism automatically tunes the tunable parameters for a demarcated code region by calculating metrics while executing the code region with different sets of tunable parameters and selecting one of the different sets based on the calculated metrics.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventor: Ruchira Sasanka