Patents by Inventor Sasikanth Manipatruni

Sasikanth Manipatruni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200194663
    Abstract: Some embodiments include apparatuses having a first magnet, a first stack of layers coupled to a first portion of the first magnet, a first layer coupled to a second portion of the first magnet, a second magnet, a second stack of layers coupled to a first portion of the second magnet, a second layer coupled to a second portion of the second magnet, a conductor coupled to the first stack of layers and to the second layer, and a conductive path coupled to the first portion of the first magnet and to the first portion of the second magnet, each of the first and second layers including a magnetoelectric material, each of the first and second stacks of layers providing an inverse spin orbit coupling effect.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Huichu Liu, Daniel Morris, Tanay Karnik, Sasikanth Manipatruni, Kaushik Vaidyanathan, Ian Young
  • Publication number: 20200194444
    Abstract: An embodiment includes a system comprising: first, second, third, fourth, fifth, and sixth layers, (a) the second, third, fourth, and fifth layers being between the first and sixth layers, and (b) the fourth layer being between the third and fifth layers; a formation between the first and second layers, the formation including: (a) a material that is non-amorphous; and (b) first and second sidewalls; a capacitor between the second and sixth layers, the capacitor including: (a) the third, fourth, and fifth layers, and (b) an electrode that includes the third layer and an additional electrode that includes the fifth layer; and a switching device between the first and sixth layers; wherein: (a) the first layer includes a metal and the sixth layer includes the metal, and (b) the fourth layer includes a Perovskite material. Other embodiments are addressed herein.
    Type: Application
    Filed: December 14, 2018
    Publication date: June 18, 2020
    Inventors: Chia-Ching Lin, Sasikanth Manipatruni, Tanay Gosavi, Dmitri Nikonov, Sou-Chi Chang, Uygar E. Avci, Ian A. Young
  • Publication number: 20200194576
    Abstract: Embodiments disclosed herein include transistor devices with complex oxide interfaces and methods of forming such devices. In an embodiment, the transistor device may comprise a substrate, and a fin extending up from the substrate. In an embodiment, a first oxide is formed over sidewall surfaces of the fin, and a second oxide is formed over the first oxide. In an embodiment, the first oxide and the second oxide are perovskite oxides with the general formula of ABO3.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Sasikanth MANIPATRUNI, Dmitri NIKONOV, Chia-Ching LIN, Tanay GOSAVI, Uygar AVCI, Ian YOUNG
  • Publication number: 20200194566
    Abstract: Systems, apparatus, and methods for initializing spin qubits with no external magnetic fields are described. An apparatus for quantum computing includes a quantum well and a pair of contacts. At least one of the contacts is formed of a ferromagnetic material. One of the contacts in the pair of contacts interfaces with a semiconductor material at a first position adjacent to the quantum well and the other contact in the pair of contacts interfaces with the semiconductor material at a second position adjacent to the quantum well. The ferromagnetic material initializes an electron or hole with a spin state prior to injection into the quantum well.
    Type: Application
    Filed: December 27, 2016
    Publication date: June 18, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth MANIPATRUNI, Ravi PILLARISETTY, Dmitri E. NIKONOV, Ian A. YOUNG, James S. CLARKE
  • Patent number: 10679782
    Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Anurag Chaudhry, Ian A. Young
  • Publication number: 20200162024
    Abstract: Embodiments may relate to a piezoresistive oscillator. The oscillator may include a fin field-effect transistor (FinFET) with a source electrode, a drain electrode, and a gate electrode. The oscillator may further include an electrical coupling coupled with the FinFET, wherein the electrical coupling electrically couples the gate electrode to the source electrode or the drain electrode. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Raseong Kim, Sasikanth Manipatruni, Ian A. Young, Gary Alfred Allen, Tanay Gosavi
  • Publication number: 20200160145
    Abstract: Embodiments may relate to a system to be used in an oscillating neural network (ONN). The system may include a control node and a plurality of nodes wirelessly communicatively coupled with a control node. A node of the plurality of nodes may be configured to identify an oscillation frequency of the node based on a weight W and an input X. The node may further be configured to transmit a wireless signal to the control node, wherein a frequency of the wireless signal oscillates based on the identified oscillation frequency. Other embodiments may be described or claimed.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Ian A. Young
  • Publication number: 20200161535
    Abstract: A memory apparatus is provided which comprises: a stack comprising a magnetic insulating material and a transition metal dichalcogenide (TMD), wherein the magnetic insulating material has a first magnetization. The stack behaves as a free magnet. The apparatus includes a fixed magnet with a second magnetization. An interconnect is further provided which comprises a spin orbit material, wherein the interconnect is adjacent to the stack.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching LIN, Tanay GOSAVI, Sasikanth MANIPATRUNI, Dmitri NIKONOV, Ian YOUNG
  • Publication number: 20200152781
    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 14, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A. Young
  • Patent number: 10642922
    Abstract: A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Phil Knag, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Abhishek Sharma, Sasikanth Manipatruni, Amrita Mathuriya, Ram Krishnamurthy, Ian A. Young
  • Publication number: 20200133990
    Abstract: Techniques are provided for efficient matrix multiplication using in-memory analog parallel processing, with applications for neural networks and artificial intelligence processors. A methodology implementing the techniques according to an embodiment includes storing two matrices in-memory. The first matrix is stored in transposed form such that the transposed first matrix has the same number of rows as the second matrix. The method further includes reading columns of the matrices from the memory in parallel, using disclosed bit line functional read operations and cross bit line functional read operations, which are employed to generate analog dot products between the columns. Each of the dot products corresponds to an element of the matrix multiplication product of the two matrices. In some embodiments, one of the matrices may be used to store neural network weighting factors, and the other matrix may be used to store input data to be processed by the neural network.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: Amrita Mathuriya, Sasikanth Manipatruni, Dmitri Nikonov, Ian Young, Ram Krishnamurthy
  • Publication number: 20200135266
    Abstract: A loaded capacitance static random-access memory (C-SRAM) is provided. The C-SRAM is configured to prevent full bit line discharge during a functional reads even where the number of bit cells on the bit lines is small. The C-SRAM includes one or more loaded capacitance structures that may take any of a variety of physical configurations designed to provide additional capacitance to the bit lines. For instance, the loaded capacitance structures may take the form of a MIM capacitor in which a ferroelectric layer is formed from one or more high K materials. In addition, the loaded capacitance structures may be positioned in a variety of locations within the C-SRAM, including the back end of line.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: Raghavan Kumar, Sasikanth Manipatruni, Gregory Chen, Huseyin Ekin Sumbul, Phil Knag, Ram Krishnamurthy, Ian Young, Mark Bohr, Amrita Mathuriya
  • Publication number: 20200134419
    Abstract: Techniques are provided for implementing a recurrent neuron (RN) using magneto-electric spin orbit (MESO) logic. An RN implementing the techniques according to an embodiment includes a first MESO device to apply a threshold function to an input signal provided at a magnetization port of the MESO device, and scale the result by a first weighting factor supplied at an input port of the MESO device to generate an RN output signal. The RN further includes a second MESO device to receive the RN output signal at a magnetization port of the second MESO device and generate a scaled previous RN state value. The scaled previous state value is a scaled and time delayed version of the RN output signal based on a second weighting factor. The RN input signal is a summation of the scaled previous state value of the RN with weighted synaptic input signals provided to the RN.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Dmitri Nikonov, Ian Young
  • Patent number: 10636840
    Abstract: An apparatus is provided which comprises: a first magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; a second magnetic junction having a fixed magnetic layer and a 4-state free magnetic layer; and a first layer of spin orbit coupling material adjacent to the first magnetic junction and the second magnetic junction via their respective 4-state free magnetic layers. Described is an apparatus which comprises a 4-state free magnetic layer; a layer of SOC material adjacent to the 4-state free magnetic layer; a first interconnect coupled to the layer of SOC material.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young
  • Patent number: 10622132
    Abstract: Described is an apparatus which comprises: an input magnet formed of one or more materials with a sufficiently high anisotropy and sufficiently low magnetic saturation to increase injection of spin currents; and a first interface layer coupled to the input magnet, wherein the first interface layer is formed of non-magnetic material such that the first interface layer and the input magnet together have sufficiently matched atomistic crystalline layers.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, David J. Michalak, Ian A. Young
  • Publication number: 20200105324
    Abstract: A magnetic tunnel junction (MTJ) for use in a magnetic spin orbit torque random access memory device (SOT MRAM) is described. Magnetic tunnel junctions described herein include a multi-magnet free layer over a spin orbit torque electrode. The multi-magnet free layer includes at least three sub-layers: a first magnetic sub-layer in direct contact with the SOT electrode having a first magnetic stability, a second magnetic sub-layer having a second magnetic stability greater than the first magnetic stability, and a magnetic coupling layer between the first and second sub-layers.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: INTEL CORPORATION
    Inventors: Angeline Smith, Sasikanth Manipatruni, MD Tofizur Rahman, Noriyuki Sato, Tanay Gasovi, Christopher Wiegand, Ian Young
  • Publication number: 20200105833
    Abstract: A DIMA semiconductor structure is disclosed. The DIMA semiconductor structure includes a frontend including a semiconductor substrate, a transistor switch of a memory cell coupled to the semiconductor substrate and a computation circuit on the periphery of the frontend coupled to the semiconductor substrate. Additionally, the DIMA includes a backend that includes an RRAM component of the memory cell that is coupled to the transistor switch.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Jack T. KAVALIEROS, Ian A. YOUNG, Ram KRISHNAMURTHY, Ravi PILLARISETTY, Sasikanth MANIPATRUNI, Gregory CHEN, Hui Jae YOO, Van H. LE, Abhishek SHARMA, Raghavan KUMAR, Huichu LIU, Phil KNAG, Huseyin SUMBUL
  • Publication number: 20200105337
    Abstract: Embodiments herein describe techniques for a semiconductor device including a memory cell. The memory cell includes a storage cell and a capacitor having a first electrode and a second electrode. The first electrode and the second electrode may be placed in a metal layer below a metal electrode coupled to one or more transistors of the storage cell. The storage cell is to store a digital value, where a voltage value of an output line of the storage cell is to be determined based on the digital value stored in the storage cell. The second electrode of the capacitor is coupled to the output line of the storage cell. The capacitor is to store a charge based on the voltage value of the output line of the storage cell. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Inventors: Gregory CHEN, Raghavan KUMAR, Huseyin Ekin SUMBUL, Phil KNAG, Ram KRISHNAMURTHY, Sasikanth MANIPATRUNI, Amrita MATHURIYA, Abhishek SHARMA, Ian A. YOUNG
  • Publication number: 20200105998
    Abstract: A perpendicular spin orbit torque (SOT) memory device includes an electrode having a spin orbit coupling material and a perpendicular magnetic tunnel junction (pMTJ) device on a portion of the electrode. The pMTJ device includes a free magnet, a fixed magnet and a tunnel barrier layer in between, where at least one of the fixed magnet or the free magnet includes two magnetic layers and a spacer layer comprising tungsten in between.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Applicant: Intel Corporation
    Inventors: Angeline SMITH, Sasikanth MANIPATRUNI, Christopher WIEGAND, Tofizur RAHMAN, Noriyuki SATO, Benjamin BUFORD
  • Patent number: 10608167
    Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Dmitri E. Nikonov, Sasikanth Manipatruni, Anurag Chaudhry, Ian A. Young