Patents by Inventor Satish K. Damaraju
Satish K. Damaraju has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11687135Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: September 20, 2021Date of Patent: June 27, 2023Assignee: Tahoe Research, Ltd.Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20220004237Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: September 20, 2021Publication date: January 6, 2022Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 11157052Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: September 23, 2019Date of Patent: October 26, 2021Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20200019221Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: September 23, 2019Publication date: January 16, 2020Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10429913Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: October 1, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10409346Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: August 7, 2018Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 10146283Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: November 6, 2017Date of Patent: December 4, 2018Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20180341305Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20180341306Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: August 7, 2018Publication date: November 29, 2018Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Publication number: 20180203694Abstract: Execution unit and floating point unit pipelines may be selectively bypassed in some cases to improve execution unit performance and reduce power consumption. For example, instructions that do not need the operations provided by those pipelines can benefit from bypassing pipelines. By performing a write as soon as the operands are read from a register file, power consumption may be reduced and performance may be increased in some embodiments. In addition, the write can be done in the same cycle with the read so that no additional cycles may be needed in some embodiments for the write after read.Type: ApplicationFiled: January 16, 2017Publication date: July 19, 2018Inventors: Subramaniam Maiyuran, Satish K. Damaraju
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Publication number: 20180059751Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: November 6, 2017Publication date: March 1, 2018Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 9823719Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: GrantFiled: May 31, 2013Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 9336008Abstract: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.Type: GrantFiled: December 28, 2011Date of Patent: May 10, 2016Assignee: INTEL CORPORATIONInventors: Satish K. Damaraju, Subramaniam Maiyuran
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Patent number: 9075741Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.Type: GrantFiled: December 16, 2011Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Altug Koker, Shailesh Shah, Aditya Navale, Murali Ramadoss, Satish K. Damaraju
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Publication number: 20140359311Abstract: In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.Type: ApplicationFiled: May 31, 2013Publication date: December 4, 2014Inventors: Sanjeev S. Jahagirdar, Satish K. Damaraju, Yun-Han Chen, Ryan D. Wells, Inder M. Sodhi, Vishram Sarurkar, Ken Drottar, Ashish V. Choubal, Rabiul Islam
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Patent number: 8713256Abstract: Embodiments described herein vary an amount of cache available for use by a processor, and an amount of power supplied to the cache and to the processor, based on the amount of cache actually being used by the processor to process data. For example, a power control unit (PCU) may monitor a last level cache (LLC) to identify if the size or amount of the cache being used by a processor to process data and to determine heuristics based on that amount. Based on the monitored amount of cache being used and the heuristics, the PCU causes a corresponding decrease or increase in an amount of the cache available for use by the processor, and a corresponding decrease or increase in an amount of power supplied to the cache and to the processor.Type: GrantFiled: December 23, 2011Date of Patent: April 29, 2014Assignee: Intel CorporationInventors: Inder M. Sodhi, Satish K. Damaraju, Sanjeev S. Jahagirdar, Ryan D. Wells
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Publication number: 20130159820Abstract: Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.Type: ApplicationFiled: December 16, 2011Publication date: June 20, 2013Inventors: Altug Koker, Shailesh Shah, Aditya Navale, Murali Ramadoss, Satish K. Damaraju
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Patent number: 8448010Abstract: The amount of data that may be transferred between a processing unit and a memory may be increased by transferring information during both the high and low phases of a clock. As one example, in a graphics processor using a general purpose register file as a memory and a mathematical box as a processing unit, the amount of data that can be transferred can be increased by transferring data during both the high and low phases of a clock.Type: GrantFiled: September 30, 2009Date of Patent: May 21, 2013Assignee: Intel CorporationInventors: Satish K. Damaraju, Subramaniam Maiyuran, Anupama Ambardar, Arindrajit Ghosh
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Patent number: 8345491Abstract: Embodiments of a memory cell comprising a voltage module configured to supply a first supply voltage and a second supply voltage, a data node programming module configured to receive the first supply voltage and to program a data node based at least in part on a write data line, and a complementary data node programming module configured to receive the second supply voltage and to program a complementary data node based at least in part on a complementary write data line, wherein the voltage module is configured such that the first supply voltage is substantially different from the second supply voltage for a period of time while the memory device is being programmed. Additional variants and embodiments may also be disclosed and claimed.Type: GrantFiled: October 26, 2011Date of Patent: January 1, 2013Assignee: Intel CorporationInventors: Satish K. Damaraju, Ak R. Ahmed, Scott E. Siers
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Publication number: 20120198208Abstract: Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an execution unit (EU) having an array of read only memory (ROM) pull down logic storing math functions. The ROM pull down logic circuit may implement single instruction, multiple data (SIMD) operations. The ROM pull down logic circuit may be operatively coupled with each of the multiple ports in a multi-port function sharing arrangement. Sharing the ROM pull down logic circuit reduces the need to duplicate logic and may result in a savings of chip area as well as a savings of power.Type: ApplicationFiled: December 28, 2011Publication date: August 2, 2012Inventors: Satish K. Damaraju, Subramaniam Maiyuran