Patents by Inventor Satoru Fujii

Satoru Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7990754
    Abstract: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2?V3<V5 and V5<V4?V1 are satisfied and (V1?V4)<VF or (V3?V2)<VF is satisfied when V5=(V1+V2)/2 is a fifth voltage V5.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: August 2, 2011
    Assignee: Panasonic Corporation
    Inventors: Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii
  • Patent number: 7964869
    Abstract: A memory element comprises a first electrode, a second electrode, and a resistance variable film 2 which is disposed between the first and second electrodes to be connected to the first and second electrodes, a resistance value of the resistance variable film 2 varying based on voltage applied between the first and second electrodes, the resistance variable film 2 includes a layer 2a made of Fe3O4 and a layer 2b made of Fe2O3 or a spinel structure oxide which is expressed as MFe2O4 (M: metal element except for Fe); and the layer 2a made of Fe3O4 is thicker than the layer 2b made of Fe2O3 or the spinel structure oxide.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Satoru Fujii, Satoru Mitani, Koichi Osano
  • Patent number: 7965539
    Abstract: A nonvolatile memory element (101) of the present invention includes a resistance variable layer (112) which intervenes between a first electrode (111) and a second electrode (113) and is configured to include at least an oxide of a metal element of VI group, V group or VI group, and when an electric pulse of a specific voltage is applied between the first voltage (111) and the second voltage (113), the resistance variable layer is turned to have a first high-resistance state or a second high-resistance state in which its resistance value is a high-resistance value RH, or a low-resistance state in which its resistance value is a low-resistance value RL.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Koichi Osano, Shunsaku Muraoka, Satoru Fujii, Kazuhiko Shimakawa
  • Patent number: 7948789
    Abstract: A resistance variable element comprises a first electrode (2), a second electrode (4), and a resistance variable layer (3) which is disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, wherein the resistance variable layer comprises material including TaOX (1.6?X?2.2), an electric resistance between the first electrode and the second electrode is lowered by application of a first voltage pulse having a first voltage between the first electrode and the second electrode, and the electric resistance between the first electrode and the second electrode is increased by application of a second voltage pulse having a second voltage of the same polarity as the first voltage, between the first electrode and the second electrode.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: May 24, 2011
    Assignee: Panasonic Corporation
    Inventors: Shunsaku Muraoka, Koichi Osano, Satoru Fujii
  • Patent number: 7920408
    Abstract: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: April 5, 2011
    Assignee: Panasonic Corporation
    Inventors: Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii, Yoshihiko Kanzawa
  • Publication number: 20110044088
    Abstract: A variable resistance nonvolatile storage device which includes (i) a semiconductor substrate (301), (ii) a variable resistance element (309) having: lower and upper electrodes (309a, 309c); and a variable resistance layer (309b) whose resistance value reversibly varies based on voltage signals each of which has a different polarity and is applied between the electrodes (309a, 309c), and (iii) a MOS transistor (317) formed on the substrate (301), wherein the variable resistance layer (309b) includes: oxygen-deficient transition metal oxide layers (309b-1, 309b-2) having compositions MOx and MOy (where x<y) and in contact with the electrodes (309a, 309c) respectively, and a diffusion layer region (302b) is connected with the lower electrode (309a) to form a memory cell (300), the region (302b) serving as a drain of the transistor (317) upon application of a voltage signal which causes a resistance change to high resistance state in the variable resistance layer (309b).
    Type: Application
    Filed: August 20, 2009
    Publication date: February 24, 2011
    Inventors: Shunsaku Muraoka, Yoshihiko Kanzawa, Satoru Mitani, Koji Katayama, Kazuhiko Shimakawa, Satoru Fujii, Takeshi Takagi
  • Publication number: 20110031465
    Abstract: A resistance variable element of the present invention comprises a first electrode (103), a second electrode (107), and a resistance variable layer which is interposed between the first electrode (103) and the second electrode (107) to contact the first electrode (103) and the second electrode (107), the resistance variable layer being configured to change in response to electric signals with different polarities which are applied between the first electrode (103) and the second electrode (107), the resistance variable layer comprising an oxygen-deficient transition metal oxide layer, and the second electrode (107) comprising platinum having minute hillocks (108).
    Type: Application
    Filed: July 22, 2009
    Publication date: February 10, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Satoru Mitani, Shunsaku Muraoka, Yoshihiko Kanzawa, Koji Katayama, Ryoko Miyanaga, Satoru Fujii, Takeshi Takaji
  • Publication number: 20100308298
    Abstract: A nonvolatile memory element includes a first electrode (103) formed on a substrate (101), a resistance variable layer (108) and a second electrode (107), wherein the resistance variable layer has a multi-layer structure including at least three layers which are a first transition metal oxide layer (104), a second transition metal oxide layer (106) which is higher in oxygen concentration than the first transition metal oxide layer (104), and a transition metal oxynitride layer (105). The second transition metal oxide layer (106) is in contact with either one of the first electrode (103) and the second electrode (107). The transition metal oxynitride layer (105) is provided between the first transition metal oxide layer (104) and the second transition metal oxide layer (106).
    Type: Application
    Filed: September 29, 2009
    Publication date: December 9, 2010
    Inventors: Takeki Ninomiya, Koji Arita, Takumi Mikawa, Satoru Fujii
  • Publication number: 20100271859
    Abstract: A nonvolatile memory element (101) of the present invention comprises a resistance variable layer (112) which intervenes between a first electrode (111) and a second electrode (113) and is configured to include at least an oxide of a metal element of VI group, V group or VI group, and when an electric pulse of a specific voltage is applied between the first voltage (111) and the second voltage (113), the resistance variable layer is turned to have a first high-resistance state or a second high-resistance state in which its resistance value is a high-resistance value RH, or a low-resistance state in which its resistance value is a low-resistance value RL.
    Type: Application
    Filed: September 25, 2008
    Publication date: October 28, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Koichi Osano, Shunsaku Muraoka, Satoru Fujii, Kazuhiko Shimakawa
  • Publication number: 20100232204
    Abstract: A resistance variable element comprises a first electrode (2), a second electrode (4), and a resistance variable layer (3) which is disposed between the first electrode and the second electrode, and electrically connected to the first electrode and the second electrode, wherein the resistance variable layer comprises material including TaOX (1.6?X?2.2), an electric resistance between the first electrode and the second electrode is lowered by application of a first voltage pulse having a first voltage between the first electrode and the second electrode, and the electric resistance between the first electrode and the second electrode is increased by application of a second voltage pulse having a second voltage of the same polarity as the first voltage, between the first electrode and the second electrode.
    Type: Application
    Filed: March 27, 2008
    Publication date: September 16, 2010
    Inventors: Shunsaku Muraoka, Koichi Osano, Satoru Fujii
  • Publication number: 20100172171
    Abstract: A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated with a selected nonvolatile memory element, apply a second voltage V2 to a second wire (BL) associated with the selected nonvolatile memory element, apply a third voltage V3 to a first wire (WL) which is not associated with the selected nonvolatile memory element and apply a fourth voltage V4 to a second wire (BL) which is not associated with the selected memory element when writing data or reading data, wherein V2?V3<V5 and V5<V4?V1 are satisfied and (V1?V4)<VF or (V3?V2)<VF is satisfied when V5=(V1+V2)/2 is a fifth voltage V5.
    Type: Application
    Filed: May 15, 2008
    Publication date: July 8, 2010
    Inventors: Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii
  • Publication number: 20100148143
    Abstract: A nonvolatile semiconductor apparatus of the present invention comprises (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (105), a resistance value of the resistance variable layer being switchable reversibly in response to an electric signal applied between the electrodes (103), (105), wherein the resistance variable layer (104) comprises an oxide containing tantalum and nitrogen.
    Type: Application
    Filed: May 16, 2008
    Publication date: June 17, 2010
    Inventors: Satoru Fujii, Yoshihiko Kanzawa, Takeshi Takagi, Kazuhiko Shimakawa
  • Publication number: 20100046273
    Abstract: Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by side in the Y direction. In each basic array plane, bit lines in even layers and bit lines in odd layers are individually connected in common. Each of selection switch elements (101 to 104) controls switching of electrical connection/non-connection between the common-connected even layer bit line and a global bit line (GBL), and each of selection switch elements (111 to 114) control switching of connection/non-connection between the common-connected odd layer bit line and the global bit line (GBL).
    Type: Application
    Filed: June 20, 2008
    Publication date: February 25, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii, Yoshihiko Kanazawa
  • Publication number: 20100027320
    Abstract: A resistance variable element (10), a resistance variable memory apparatus, and a resistance variable apparatus, comprise a first electrode (2), a second electrode (4), and a resistance variable layer (3) which is disposed between the first electrode (2) and the second electrode (4) and is electrically connected to the first electrode (2) and to the second electrode (4), wherein the resistance variable layer (3) contains a material having a spinel structure which is expressed as a chemical formula of (NixFe1-x) Fe2O4, X being not smaller than 0.35 and not larger than 0.
    Type: Application
    Filed: December 20, 2007
    Publication date: February 4, 2010
    Inventors: Shunsaku Muraoka, Kiochi Osano, Satoru Fujii
  • Publication number: 20100008127
    Abstract: A resistance variable element of the present invention and a resistance variable memory apparatus using the resistance variable element are a resistance variable element (10) including a first electrode, a second electrode, and a resistance variable layer (3) provided between the first electrode (2) and the second electrode (4) to be electrically connected to the first electrode (2) and the second electrode (4), wherein the resistance variable layer (3) contains a material having a spinel structure represented by a chemical formula of (ZnxFe1-x)Fe2O4, and the resistance variable element (10) has a feature that an electrical resistance between the first electrode (2) and the second electrode (4) increases by applying a first voltage pulse to between the first electrode (2) and the second electrode (4), and the electrical resistance between the first electrode (2) and the second electrode (4) decreases by applying a second voltage pulse whose polarity is the same as the first voltage pulse to between the first
    Type: Application
    Filed: December 20, 2007
    Publication date: January 14, 2010
    Inventors: Shunsaku Muraoka, Kolchi Osano, Satoru Fujii
  • Publication number: 20090321709
    Abstract: A memory element comprises a first electrode, a second electrode, and a resistance variable film 2 which is disposed between the first and second electrodes to be connected to the first and second electrodes, a resistance value of the resistance variable film 2 varying based on voltage applied between the first and second electrodes, the resistance variable film 2 includes a layer 2a made of Fe3O4 and a layer 2b made of Fe2O3 or a spinel structure oxide which is expressed as MFe2O4 (M: metal element except for Fe); and the layer 2a made of Fe3O4 is thicker than the layer 2b made of Fe2O3 or the spinel structure oxide.
    Type: Application
    Filed: August 17, 2007
    Publication date: December 31, 2009
    Inventors: Shunsaku Muraoka, Satoru Fujii, Satoru Mitani, Koichi Osano
  • Publication number: 20090283736
    Abstract: A nonvolatile memory element comprises a first electrode layer (103), a second electrode (107), and a resistance variable layer (106) which is disposed between the first electrode layer (103) and the second electrode layer (107), a resistance value of the resistance variable layer varying reversibly according to electric signals having different polarities which are applied between the electrodes (103), (107), wherein the resistance variable layer (106) has a first region comprising a first oxygen-deficient tantalum oxide having a composition represented by TaOx (0<x<2.5) and a second region comprising a second oxygen-deficient tantalum oxide having a composition represented by TaOy (x<y<2.5), the first region and the second region being arranged in a thickness direction of the resistance variable layer.
    Type: Application
    Filed: March 26, 2008
    Publication date: November 19, 2009
    Inventors: Yoshihiko Kanzawa, Koji Katayama, Satoru Fujii, Shunsaku Muraoka, Koichi Osano, Satoru Mitani, Ryoko Miyanaga, Takeshi Takagi, Kazuhlko Shimakawa
  • Publication number: 20090250678
    Abstract: A nonvolatile memory apparatus comprises a first electrode (111), a second electrode (112), a variable resistance layer (113) which is disposed between the electrodes, a resistance value of the variable resistance layer reversibly varying between a plurality of resistance states based on an electric signal applied between the electrodes, a first terminal (103) connected to the first electrode, and a second terminal (104) connected to the second terminal. The variable resistance layer comprises at least a tantalum oxide, and is configured to satisfy 0<x<2.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 8, 2009
    Inventors: Koichi Osano, Satoru Fujii, Shunsaku Muraoka
  • Publication number: 20090224224
    Abstract: A nonvolatile memory element of the present invention comprises a first electrode (103), a second electrode (105), and a resistance variable layer (104) disposed between the first electrode (103) and the second electrode (104), a resistance value of the resistance variable layer varying reversibly according to an electric signal applied between the electrodes (103),(105), and the resistance variable layer (104) comprises at least a tantalum oxide, and is configured to satisfy 0<x<2.5 when the tantalum oxide is represented by TaOx.
    Type: Application
    Filed: October 24, 2007
    Publication date: September 10, 2009
    Inventors: Satoru Fujii, Takeshi Takagi, Shunsaku Muraoka, Koichi Osano, Kazuhiko Shimakawa
  • Patent number: 7318974
    Abstract: A polymer electrolyte fuel cell of the present invention includes a hydrogen ion-conductive polymer electrolyte membrane, an anode and a cathode sandwiching the hydrogen ion-conductive polymer electrolyte membrane, an anode-side conductive separator plate having a gas flow channel for supplying a fuel gas to the anode, and a cathode-side conductive separator plate having a gas flow channel for supplying an oxidant gas to the cathode.
    Type: Grant
    Filed: April 9, 2002
    Date of Patent: January 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideo Ohara, Hiroki Kusakabe, Masayo Sugou, legal representative, Nobuhiro Hase, Shinsuke Takeguchi, Yoshiaki Yamamoto, Toshihiro Matsumoto, Satoru Fujii, Kazuhito Hatoh, Masato Hosaka, Junji Niikura, Kazufumi Nishida, Teruhisa Kanbara, Tatsuto Yamazaki, deceased