Abstract: A decoder including a Viterbi decoding section for Viterbi-decoding data and a fixed delay tree search decoding section for fixed-delay-tree-search-decoding the data includes a metric calculation circuit used by both the Viterbi decoding section and the fixed delay tree search decoding section.

Abstract: An ITR (Interpolated Timing Recovery) data reproducing apparatus capable of acquiring an excellent reproduction output waveform with less distortion and updating sampling timing at high speed with a simple configuration is provided. Each sampling period (Ts) of a desired interpolation function f(t) is split into a plurality of periods, linear interpolation is performed for each of the split periods, and data at each interpolation point within each of the split periods is calculated. In addition, only a binary integer representation part is extracted as a quotient obtained by performing integer division of sampling timing for a sampling period, and only input sampling data (Ds) for a number of the binary integer representation part is captured into an interpolation filter to operate a pipeline.

Abstract: A modulation apparatus includes: a modulation section that modulates, in accordance with a correlation table where a data sequence with a predetermined number of bits is associated with a code sequence with a predetermined number of bits, the data sequence into the code sequence to allow a predetermined demodulation section to demodulate the code sequence into the data sequence in accordance with the correlation table, wherein the code sequence is, on NRZI method, a MSN code sequence where a null point of a frequency spectrum on a recording channel or communication channel of the code sequence is matched with a null point of a frequency spectrum of a PR equalized signal including the code sequence and a minimum run length is limited to be greater or equal to one.

Abstract: A synchronizing apparatus, which controls, by a PLL circuit, a sampling clock to be used to sample input data and synchronizes a phase of the sampling clock with a target phase that is desirable for sampling the input data, includes: phase error detection means for detecting a phase error from sampling data and the sampling clock, the sampling data being sampled from the input data at timing of the sampling clock; frequency error detection means for detecting, based on a differential coefficient obtained as a result of detecting the phase error, a frequency error; and frequency correction means for correcting a frequency of the sampling clock such that the detected frequency error becomes close to zero by adding a frequency correction value to an integral term of a loop filter of the PLL circuit, the frequency correction value being calculated based on the frequency error.

Abstract: An ITR (Interpolated Timing Recovery) data reproducing apparatus capable of acquiring an excellent reproduction output waveform with less distortion and updating sampling timing at high speed with a simple configuration is provided. Each sampling period (Ts) of a desired interpolation function f(t) is split into a plurality of periods, linear interpolation is performed for each of the split periods, and data at each interpolation point within each of the split periods is calculated. In addition, only a binary integer representation part is extracted as a quotient obtained by performing integer division of sampling timing for a sampling period, and only input sampling data (Ds) for a number of the binary integer representation part is captured into an interpolation filter to operate a pipeline.

Abstract: A decoder including a Viterbi decoding section for Viterbi-decoding data and a fixed delay tree search decoding section for fixed-delay-tree-search-decoding the data includes a metric calculation circuit used by both the Viterbi decoding section and the fixed delay tree search decoding section.

Abstract: The present invention provides an adaptive equalizing apparatus that can positively remove the leading ISI, and make a maximum-likelihood decoding and an optimum equalization on the basis of the result of the maximum-likelihood decoding with consideration being given to the asymmetry of an input waveform. The adaptive equalizing apparatus includes a feedforward filter to filter the read signal, a maximum-likelihood decoder making maximum-likelihood decoding of the signal filtered by the feedforward filter to generate the binary signal, a feedback filter to filter the binary signal supplied from the maximum-likelihood decoder, a delay unit delaying the signal filtered by the feedforward filter by a processing time of the maximum-likelihood decoder, and a subtracter subtracting the signal supplied from the feedback filter from the signal supplied from the delay unit.

Abstract: For a waveform containing a partial response and distortion in only the leading-edge portion of inter-symbol interference (ISI) of a waveform equalized by a prior-stage feedforward filter (FFF) so as to satisfy causality, equalization that does not consider postcursor ISI subsequent to the partial response is performed; a feedback filter (FBF) uses a determination result of a decoding device to generate a response for the distortion of the partial response portion and the postcursor ISI; and the result is subtracted from an FFF output delayed by the amount of determination delay to create a desired partial response waveform. As a method for equalization that satisfies causality, a least mean square algorithm is applied to the partial response waveform generated as described above.

Abstract: In a waveform equalizer for a communication apparatus, a magnetic recording apparatus, or an optical recording/reproducing apparatus, a feed-forward filter (FFF) is provided and, at a subsequent stage, a decision feedback equalizer (DFE) or a fixed delay tree search/decision feedback equalizer (FDTS/DFE) employing FDTS for a determination unit is provided. Partial response (PR) is performed on only a first portion of inter-symbol interference (ISI) of a waveform equalized by the FFF and equalization that does not consider subsequent response (i.e., trailing-edge ISI) is performed. A feed-back filter (FBF) generates a response for the trailing-edge ISI and the DFE structure subtracts the generated response from a response provided by the FFF so that a result becomes a partial response.

Abstract: The present invention provides an excellent waveform equalization apparatus and its method realizing a PR1 equalizer reducing circuit scale and reducing power consumption. It is known that in a high frequency region proximate to Nyquist frequency, emphasis of an amplitude characteristic is smaller in Class 1 (PR1) than in Class 4 (PR4) of Partial Response. Hence, there is constituted a waveform equalizing apparatus satisfying PR1 equalization reference by a combination of an integrator for low frequency region emphasis and a filter constituted for PR4. By such a constitution, circuit scale can be reduced more than that of conventional PR1 equalizer and power consumption can be reduced.

Abstract: It is an object to save a circuit scale and simultaneously improve sync-byte pattern detecting performance. A Viterbi detecting circuit executes first the detecting operation without relation to time limitation. A sync-byte detecting circuit detects the sync-byte from the detection result supplied from a path memory built in the Viterbi detecting circuit and also outputs the detected signal to switches and Viterbi detecting circuit in the timing to start detection of user data. The Viterbi circuit initializes (resets) the path memory and path metric corresponding to the detected signal supplied from the sync-byte detecting circuit and also starts subsequently the trellis Viterbi detection accompanied by the time limitation of the trellis path to the data supplied from the switch.

Abstract: In order to implement encoding which is proof against noise and distortion, there is provided an encoder for coding a train of input codes characterized in that 3 consecutively transiting consistent codes starting from either an odd-numbered or an even-numbered channel clock pulse of a channel clock signal and all 4 consecutively transiting consistent codes are restricted to produce a train of output codes and the number of produced codes in the train is made even.

Abstract: The present invention relates to an apparatus for azimuth-recording data on a magnetic recording medium. Heads (13a) and (13b) having azimuth angles different from each other are used and data are recorded on and reproduced from a plurality of adjacent tilted recording tracks on a magnetic tape T. A recording-system encoder (23) converts data to a code sequence in which null points of frequency spectrums are respectively provided at null points of waveform equalization characteristics of partial responses such as PR1, PR4, etc. For example, record-coding using a 8/10MSN code is performed. A reproduction-system equalizing circuit (28) performs waveform equalization based on the partial responses. Further, a data detector (29) detects the data by a Viterbi coding method for executing state transition during which the characteristic of the code sequence is adopted.

Abstract: It is intended to reduce the rate of occurrence of prediction value judgment errors. Where a prediction value x'.sub.n-1 of a 1-clock preceding code is 0, a judgment circuit 1 outputs a value "1" as a prediction value x'.sub.n if a reproduction signal value y.sub.n sampled at time n is greater than or equal to a threshold value .eta. that is supplied from a threshold value generating circuit 6, and outputs a value "-1" as the prediction value x'.sub.n if y.sub.n <.eta.. Where x'.sub.n-1 is not 0, the judgment circuit 1 outputs a value "0" as the prediction value x'.sub.n. Therefore, the control circuit 1 outputs a value "0" every other clock as a prediction value. During the interval between the first two clocks, the threshold value .eta. is set at 0. Then, when supplied with codes of a given pattern that are arranged at the start, a switch 2 selects the prediction value x'.sub.n that is supplied from the judgment circuit 1. An operation circuit 16 calculates a phase error .DELTA..tau..sub.