Abstract: A signal transmit-receive device of the invention reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group, and for running a loopback test on a signal transmit-receive device. The loopback test circuit uses an error detecting circuit, a test signal producing circuit, and a wiring for transmitting error information. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern. The test signal producing circuit produces the test signal pattern based on error information. If an error is detected, the error signal is transmitted to the test signal producing circuit through the wiring. The test signal producing circuit produces a predetermined test signal pattern if the error signal DE has an L level; upon receiving H level, it sends back the predetermined test signal pattern to the first communication device.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: A signal transmit-receive device that reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group and for running a loopback test on a signal transmit-receive device for signal communication, and reduces installation costs and power consumption. The new loopback test circuit uses an error detecting circuit within the transmitting circuit IC, a test signal producing circuit within the receiving circuit IC, and a wiring for transmitting error information from the transmitting circuit to the receiving circuit. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern to detect errors. The test signal producing circuit produces a test signal pattern defined in advance by the first communication device, and can invert any bits of the test signal pattern, based on error information.

Abstract: A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.

Abstract: A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.

Abstract: To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested.

Abstract: A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits.

Abstract: A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.

Abstract: A semiconductor integrated circuit device includes an element separating first and second grooves formed to surround active regions to be formed with a semiconductor element. In addition a third groove is formed to surround at least a portion of the first groove, when viewed from a plane view. In the semiconductor integrated circuit device, the active regions and an element separating region of a silicon layer are insulated from each other by the separating grooves extending from the main surface of the silicon layer to an underlying insulating layer, and are fed with a common fixed potential.

Abstract: In a gate array with a RAM which is disposed between first and second logic circuit blocks each of which having plural logic gates, by-pass signal lines which interconnect the logic circuit blocks are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines, such as word lines of the RAM, formed from a layer which is adjacent to the by-pass signal lines are disposed, with respect to a plan view layout arrangement of the main surface of a chip, so as to intersect the latter at right angles. In addition, interconnection pitches of signal lines in different wiring layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.