Abstract: A semiconductor integrated circuit device has a circuit construction which is devised with an output circuit for feeding an output current to an operating supply voltage in response to an output signal of a current switch circuit responding to an input signal. A constant current element for producing the operating current of the current switch circuit is fed with a constant voltage through a resistance element. A capacitor is coupled between the input of the constant current element and the operating supply voltage so that it constructs a time constant circuit together with the resistance element. The time constant circuit has a time constant set longer than the period of the output signal of the output circuit.

Abstract: A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Abstract: Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.

Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layer which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Abstract: A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.

Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Abstract: Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Abstract: A thermoplastic and elastomeric composition comprising a polyamide resin and a rubber component, wherein the rubber component is dispersed in the form of crosslinked particles in the polyamide resin.

Abstract: In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Abstract: A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

Abstract: Articles having shape recovering properties and methods of using them are disclosed. An article is formed from a composition containing a norbornene polymer by forming said polymer into an article having a first shape, then deforming the article in the solid state to a second shape and cooling the article to a first temperature at or below the glass transition temperature of the polymer to retain said second shape, and finally heating said article to a temperature above the first temperature to recover the first shape.