Patents by Inventor Satoru Ito
Satoru Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9054305Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.Type: GrantFiled: March 13, 2014Date of Patent: June 9, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoru Ito, Yoshio Kawashima, Yukio Hayakawa, Takumi Mikawa
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Patent number: 9006701Abstract: A non-volatile memory device comprises first wires on and above a first plane; second wires extending in a direction crossing the first wires, on and above a second plane, third wires extending in parallel with the second wires on and above a fourth plane, and memory cells provided to correspond to three-dimensional cross-points of the first wires and the third wires, respectively, each of the memory cells including a transistor and a variable resistance element, the transistor including a first main electrode, a second main electrode, and a control electrode, the variable resistance element being placed on and above a third plane and including a lower electrode, an upper electrode and a variable resistance layer, wherein the upper electrode is connected to corresponding one of the third wires; and further comprises a first contact plug extending from the first main electrode to the second plane and connected to corresponding one of the second wires; a second contact plug extending from the second main electrType: GrantFiled: October 15, 2013Date of Patent: April 14, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Satoru Ito, Takumi Mikawa
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Patent number: 8981333Abstract: Provided is a nonvolatile semiconductor memory device including a variable resistance element in which a parasitic resistance between the lower electrode and the variable resistance layer included in the variable resistance element is reduced. The nonvolatile semiconductor memory device includes: a substrate; and a variable resistance elementformed on the substrate, wherein the variable resistance elementincludes a lower electrode layer formed on the substrate, a variable resistance layer formed on the lower electrode layer, and an upper electrode layer formed on the variable resistance layer, the lower electrode layer includes at least a first conductive layer and a second conductive layer which is formed on the first conductive layer and is in contact with the variable resistance layer, and the first conductive layer includes an oxidatively degraded layer which is formed on an upper surface of the first conductive layer due to oxidization of the first conductive layer.Type: GrantFiled: October 10, 2012Date of Patent: March 17, 2015Assignee: Panasonic Intellectual Property Management, Co., Ltd.Inventors: Satoru Fujii, Satoru Ito, Takumi Mikawa
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Publication number: 20140375295Abstract: A DC-DC converter includes: an error amplifier for outputting an error between an output voltage and a predetermined voltage; a phase compensation impedance element for accumulating the error across one end to generate an error phase; a determination unit for determining whether the voltage output by the error amplifier is higher, or lower than a reference voltage that is consonant with the predetermined voltage, and outputting a determination signal indicating determination results; and a voltage setting unit for setting a voltage for one end of the phase compensation impedance element higher than a lower output voltage limit for the error amplifier when the determination signal indicates that the voltage output by the error amplifier is lower than the reference voltage, or for canceling setting of the voltage when the determination signal indicates that the voltage output by the error amplifier is higher than the reference voltage.Type: ApplicationFiled: April 26, 2013Publication date: December 25, 2014Applicant: Asahi Kasei Microdevices CorporationInventor: Satoru Ito
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Publication number: 20140362357Abstract: The present invention provides an exposure apparatus which exposes each of a plurality of shot regions on a substrate, comprising a substrate stage configured to be movable while holding the substrate, and a control unit, wherein the plurality of shot regions include a first shot region, and a second shot region which is exposed next to the first shot region, and the control unit drives the substrate stage in accordance with drive information of the substrate stage in a period until exposure of the second shot region starts after an end of exposing the first shot region, and when an exposure condition for exposing the second shot region is not satisfied in the period, the control unit drives again the substrate stage in accordance with the drive information and then exposes the second shot region.Type: ApplicationFiled: June 9, 2014Publication date: December 11, 2014Inventor: Satoru Ito
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Publication number: 20140343035Abstract: The present invention provides a compound represented by Formula (I) (wherein R1, X1, X2, Y, and Z are as defined in the specification), or a salt thereof.Type: ApplicationFiled: January 17, 2013Publication date: November 20, 2014Inventors: Takeshi Sagara, Satoru Ito, Sachie Otsuki, Hiroshi Sootome
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Patent number: 8889666Abstract: The present invention provides a new compound that has an inhibitory action against EGFR and that has cell growth inhibitory effects. The present invention further provides a pharmaceutical preparation useful for preventing and/or treating cancer, based on the EGFR inhibitory effect of the compound. A compound represented by the following Formula (I) or a salt thereof.Type: GrantFiled: February 22, 2013Date of Patent: November 18, 2014Assignee: Taiho Pharmaceutical Co., Ltd.Inventors: Takeshi Sagara, Satoru Ito, Sachie Otsuki, Katsumasa Nonoshita
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Publication number: 20140307145Abstract: An imaging apparatus according to the present invention is an imaging apparatus performing live-view display by generating image data using an exposure parameter calculated from a brightness value in a photometric area for the live-view display which is different from a photometric area for focus adjustment when not performing the focus adjustment, and performing the live-view display also when performing the focus adjustment, and includes: a focus adjustment brightness value calculation section comparing a first brightness value in the photometric area for the live-view display with a second brightness value in the photometric area for the focus adjustment, correcting the first brightness value according to a comparison result, and calculating a brightness value for obtaining the image data for the focus adjustment; an imaging section obtaining the image data by performing exposure using the brightness value calculated by the focus adjustment brightness value calculation section; a focus adjustment section pType: ApplicationFiled: April 15, 2014Publication date: October 16, 2014Applicant: Olympus CorporationInventor: Satoru ITO
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Publication number: 20140264249Abstract: A nonvolatile memory device includes a plurality of nonvolatile memory elements each having an upper electrode, a variable resistance layer, and a lower electrode; a first insulating layer embedding the plurality of nonvolatile memory elements, and ranging from a lowermost part of the lower electrode to a position higher than an uppermost part of the upper electrode in each of the nonvolatile memory elements; a second insulating layer being formed on the first insulating layer, and having an average size of vacancies larger than an average size of vacancies included in the first insulating layer, or having an average carbon concentration higher than an average carbon concentration of the first insulating layer; and a conductive layer penetrating the second insulating layer and a part of the first insulating layer and being connected to at least one of the upper electrodes included in the nonvolatile memory elements.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Panasonic CorporationInventors: Satoru ITO, Yoshio KAWASHIMA, Yukio HAYAKAWA, Takumi MIKAWA
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Patent number: 8823867Abstract: A camera of the present invention comprises a contrast detection section for detecting a contrast value, an assist light section for irradiating a subject by emitting light at a first luminance amount or a second luminance amount that is dimmer than the first luminance amount, and a control section for moving the photographing lens and detecting a focus position of the photographing lens based on contrast values detected by the contrast detection section, wherein the control section causes the assist light section to emit assist light in a first luminance amount or a second luminance amount, and detects a focus position of the photographing lens based on one of a first contrast value detected in a state where the assist light section emits light in the first luminance amount, or a second contrast value detected in a state where the assist light section emits light in the second luminance amount.Type: GrantFiled: July 6, 2012Date of Patent: September 2, 2014Assignee: Olympus Imaging Corp.Inventor: Satoru Ito
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Publication number: 20140225054Abstract: A method of manufacturing a non-volatile memory element includes forming a first electrode; forming a variable resistance layer; and forming a second electrode. Forming the variable resistance layer includes forming a third metal oxide layer having a third metal oxide, forming a second metal oxide layer having a second metal oxide, and forming a first metal oxide layer e having a first metal oxide; wherein the variable resistance layer reversibly changes its resistance value in response to an electric signal applied between the first electrode and the second electrode; the first metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the second metal oxide is lower in degree of oxygen deficiency than the third metal oxide; the third metal oxide is an oxygen-deficient metal oxide; and the first metal oxide layer is different in density from the second metal oxide layer.Type: ApplicationFiled: February 6, 2014Publication date: August 14, 2014Applicant: PANASONIC CORPORATIONInventors: Shinichi YONEDA, Satoru ITO, Satoru FUJII
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Publication number: 20140216515Abstract: A thermal stress of electrode members (121 to 123) due to an operation temperature may be relaxed by thermal stress relaxation layers (141 to 144), and thus peeling of the electrode members (121 to 123) due to thermal stress at the operation temperature may be prevented in a satisfactory manner. Furthermore, diffusion of a constituent component of the thermoelectric conversion members (111 and 112) due to the operation temperature and the like may be prevented by diffusion prevention layers (151 to 154), and thus durability and stability of the thermoelectric conversion module (100) may be improved.Type: ApplicationFiled: November 22, 2011Publication date: August 7, 2014Applicant: FURUKAWA CO., LTD.Inventors: Takahiro Ochi, Shogo Suzuki, Masaaki Kikuchi, Huiyuan Geng, Satoru Ito, Junqing Guo
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Patent number: 8796779Abstract: A first MIS transistor and a second MIS transistor of the same conductivity type are formed on an identical semiconductor substrate. An interface layer included in a gate insulating film of the first MIS transistor has a thickness larger than that of an interface layer included in a gate insulating film of the second MIS transistor.Type: GrantFiled: October 31, 2012Date of Patent: August 5, 2014Assignee: Panasonic CorporationInventors: Satoru Ito, Yoshiya Moriyama, Hiroshi Ohkawa, Susumu Akamatsu
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Publication number: 20140204266Abstract: A focus adjustment unit according to the present invention has an imaging section configured to generate an image signal by forming and capturing an optical image on an image sensor by an optical system including a focusing lens, and performs focus adjustment based on a focus detection signal relating to a focus detection area set within an imaging area, the focus adjustment unit comprising a focusing lens position detection section configured to detect a position of the focusing lens, a storage section configured to store information on an image magnification change of the optical system along with movement of the focusing lens, and a focus detection area setting section configured to set a focus detection area within the imaging area, wherein the focus detection area setting section sets the focus detection area based on the position of the focusing lens and the information on an image magnification change.Type: ApplicationFiled: January 16, 2014Publication date: July 24, 2014Applicant: Olympus Imaging Corp.Inventor: Satoru ITO
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Patent number: 8786762Abstract: An imaging device of the present invention comprises an imaging section for forming a subject image using a photographing lens and generating image data, a contrast detection section for detecting contrast values corresponding to contrast of the subject image, for every position of the photographing lens, based on the image data, a subject brightness detection section for detecting brightness evaluation values corresponding to subject brightness of the subject image for every position of the photographing lens, based on the image data, a correction section for correcting the contrast values depending on a brightness evaluation value for a corresponding position of the photographing lens and calculating corrected contrast value, and a focus detection section for detecting a focus position of the photographing lens based on the corrected contrast values that have been corrected by the correction section.Type: GrantFiled: February 23, 2011Date of Patent: July 22, 2014Assignee: Olympus Imaging Corp.Inventor: Satoru Ito
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Publication number: 20140197368Abstract: A nonvolatile memory element including: a first electrode; a second electrode; a variable resistance layer that is between the first electrode and the second electrode and includes, as stacked layers, a first variable resistance layer connected to the first electrode and a second variable resistance layer connected to the second electrode; and a side wall protecting layer that has oxygen barrier properties and covers a side surface of the variable resistance layer. The first variable resistance layer includes a first metal oxide and a third metal oxide formed around the first metal oxide and having an oxygen deficiency lower than that of the first metal oxide, and the second variable resistance layer includes a second metal oxide having an oxygen deficiency lower than that of the first metal oxide.Type: ApplicationFiled: September 10, 2012Publication date: July 17, 2014Applicant: Panasonic CorporationInventors: Shinichi Yoneda, Takumi Mikawa, Satoru Ito, Yukio Hayakawa, Atsushi Himeno
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Patent number: 8779406Abstract: A nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer positioned between the first electrode and the second electrode. The variable resistance layer has a resistance state which reversibly changes based on an electrical signal applied between the first electrode and the second electrode. The variable resistance layer includes a first variable resistance layer having a first metal oxide and a second variable resistance layer having a second metal oxide. The second variable resistance layer includes a metal-metal bonding region including a metal bond of metal atoms included in the second metal oxide, and the second metal oxide has a low degree of oxygen deficiency and a high resistance value compared to the first metal oxide.Type: GrantFiled: January 18, 2013Date of Patent: July 15, 2014Assignee: Panasonic CorporationInventors: Satoru Ito, Satoru Fujii, Shinichi Yoneda, Takumi Mikawa
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Patent number: 8766877Abstract: A communication system in trains comprises a control data communication device 400 and an image data communication device 300 installed in each of the cars. The control data communication device 400 transmits train operation information, train location information, control instructions of train-mounted apparatuses, and the like. The image data communication device 300 transmits image information such as moving images and still images, audio information such as in-train announcement, textual information for caption display, and operation log information of apparatuses, which form the contents, to a display unit 200 installed in each of the cars and to apparatuses 500 such as a telephone. The display unit 200 switches the display on the screen in accordance with train control information transmitted from the control data communication device 400 through the image data communication device 300.Type: GrantFiled: January 24, 2008Date of Patent: July 1, 2014Assignee: Hitachi, Ltd.Inventors: Nao Saito, Setsuo Arita, Satoru Ito, Kazunori Ayabe, Yukio Sagawa
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Publication number: 20140175369Abstract: A method of manufacturing a non-volatile memory device comprises: forming a first electrode layer; a variable resistance material layer, a second electrode layer; and a hard mask layer, forming a first resist mask extending in a first direction on the hard mask layer; forming a first hard mask extending in the first direction by etching the hard mask layer using the first resist mask; forming a second resist mask extending in a second direction, on the first hard mask such that the width of the second resist mask is greater than the width of the first resist mask; forming a second hard mask by etching the first hard mask using the second resist mask; and forming a variable resistance element by patterning, by etching the second electrode layer, the variable resistance material layer and the first electrode layer using the second hard mask.Type: ApplicationFiled: December 23, 2013Publication date: June 26, 2014Applicant: PANASONIC CORPORATIONInventors: Hideaki MURASE, Satoru ITO, Yoshio KAWASHIMA, Takumi MIKAWA
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Publication number: 20140138607Abstract: A non-volatile memory device comprises first wires on and above a first plane; second wires extending in a direction crossing the first wires, on and above a second plane, third wires extending in parallel with the second wires on and above a fourth plane, and memory cells provided to correspond to three-dimensional cross-points of the first wires and the third wires, respectively, each of the memory cells including a transistor and a variable resistance element, the transistor including a first main electrode, a second main electrode, and a control electrode, the variable resistance element being placed on and above a third plane and including a lower electrode, an upper electrode and a variable resistance layer, wherein the upper electrode is connected to corresponding one of the third wires; and further comprises a first contact plug extending from the first main electrode to the second plane and connected to corresponding one of the second wires; a second contact plug extending from the second main electrType: ApplicationFiled: October 15, 2013Publication date: May 22, 2014Applicant: PANASONIC CORPORATIONInventors: Satoru ITO, Takumi MIKAWA