Patents by Inventor Satoru Kawamoto
Satoru Kawamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953904Abstract: There is provided a control device including an image display unit configured to acquire, from a flying body, an image captured by an imaging device provided in the flying body and to display the image, and a flight instruction generation unit configured to generate a flight instruction for the flying body based on content of an operation performed with respect to the image captured by the imaging device and displayed by the image display unit.Type: GrantFiled: July 15, 2022Date of Patent: April 9, 2024Assignee: SONY GROUP CORPORATIONInventors: Kohtaro Sabe, Yasunori Kawanami, Kenta Kawamoto, Tsutomu Sawada, Satoru Shimizu, Peter Duerr, Yuki Yamamoto
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Patent number: 8029879Abstract: A display device includes a pair of glass substrates. On the side of each of the pair of glass substrates, a press mark is formed between a first end of each of the pair of glass substrates and a position at least 0.3 mm but no more than 3 mm away from the first end, another press mark is formed between a second end of each of the pair of glass substrates and a position at least 0.3 mm but no more than 3 mm away from the second end, a scribing groove having a predetermined scribing amount is formed between the press marks, and there are rib marks in the scribing groove.Type: GrantFiled: April 17, 2008Date of Patent: October 4, 2011Assignee: Sony CorporationInventor: Satoru Kawamoto
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Patent number: 8023341Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.Type: GrantFiled: October 12, 2010Date of Patent: September 20, 2011Assignee: Spansion LLCInventors: Shozo Kawabata, Kenji Shibata, Takaaki Furuyama, Satoru Kawamoto
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Publication number: 20110026287Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.Type: ApplicationFiled: October 12, 2010Publication date: February 3, 2011Inventors: Shozo KAWABATA, Kenji SHIBATA, Takaaki FURUYAMA, Satoru KAWAMOTO
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Patent number: 7881142Abstract: A storage device and its control method are described, according to which a bias voltage to be supplied to a memory cell array is selected from boosted voltages which are increased from an external voltage and non-boosted voltages which are not increased from the external voltage. In the period during which a DC-DC converter section supplies a boosted voltage increased from the external voltage to an internal bias line for supplying a bias voltage to the memory cell array, a non-boosted voltage supply section for supplying a non-boosted voltage equal to or less than the external voltage is in its inactive state. In the period during which the non-boosted voltage supply section supplies a non-boosted voltage to the internal bias line, the DC-DC converter section is in its inactive state.Type: GrantFiled: September 29, 2006Date of Patent: February 1, 2011Assignee: Spansion LLCInventors: Hideki Arakawa, Satoru Kawamoto
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Patent number: 7813154Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.Type: GrantFiled: August 27, 2008Date of Patent: October 12, 2010Assignee: Spansion LLCInventors: Shozo Kawabata, Kenji Shibata, Takaaki Furuyama, Satoru Kawamoto
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Patent number: 7764560Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.Type: GrantFiled: June 25, 2008Date of Patent: July 27, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hajime Sato, Yuji Nakagawa, Satoru Kawamoto
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Patent number: 7739559Abstract: A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.Type: GrantFiled: May 30, 2006Date of Patent: June 15, 2010Assignee: Spansion LLCInventors: Norikatsu Suzuki, Makoto Niimi, Satoru Kawamoto
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Patent number: 7675801Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.Type: GrantFiled: November 18, 2008Date of Patent: March 9, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hajime Sato, Yuji Nakagawa, Satoru Kawamoto
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Patent number: 7580308Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.Type: GrantFiled: June 19, 2007Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Hajime Sato, Yuji Nakagawa, Satoru Kawamoto
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Publication number: 20090150635Abstract: Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.Type: ApplicationFiled: June 12, 2008Publication date: June 11, 2009Inventors: Kenji SHIBATA, Mitsuhiro NAGAO, Satoru KAWAMOTO
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Patent number: 7514781Abstract: A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.Type: GrantFiled: November 21, 2006Date of Patent: April 7, 2009Assignee: DENSO CORPORATIONInventor: Satoru Kawamoto
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Publication number: 20090073793Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.Type: ApplicationFiled: November 18, 2008Publication date: March 19, 2009Applicant: FUJITSU LIMITEDInventors: Hajime Sato, Yuji Nakagawa, Satoru Kawamoto
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Patent number: 7495990Abstract: It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k?1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.Type: GrantFiled: June 4, 2007Date of Patent: February 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kazufumi Komura, Yoshiharu Kato, Satoru Kawamoto
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Patent number: 7492232Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.Type: GrantFiled: May 24, 2007Date of Patent: February 17, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yasushige Ogawa, Satoru Kawamoto
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Publication number: 20080316787Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.Type: ApplicationFiled: August 27, 2008Publication date: December 25, 2008Inventors: Shozo KAWABATA, Kenji Shibata, Takaaki Furuyama, Satoru Kawamoto
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Publication number: 20080311817Abstract: A display device includes a pair of glass substrates. On the side of each of the pair of glass substrates, a press mark is formed between a first end of each of the pair of glass substrates and a position at least 0.3 mm but no more than 3 mm away from the first end, another press mark is formed between a second end of each of the pair of glass substrates and a position at least 0.3 mm but no more than 3 mm away from the second end, a scribing groove having a predetermined scribing amount is formed between the press marks, and there are rib marks in the scribing groove.Type: ApplicationFiled: April 17, 2008Publication date: December 18, 2008Applicant: EPSON IMAGING DEVICES CORPORATIONInventor: Satoru KAWAMOTO
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Publication number: 20080253213Abstract: A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized.Type: ApplicationFiled: June 25, 2008Publication date: October 16, 2008Applicant: Fujitsu LimitedInventors: Hajime Sato, Yuji Nakagawa, Satoru Kawamoto
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Patent number: 7433219Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.Type: GrantFiled: January 27, 2006Date of Patent: October 7, 2008Assignee: Spansion LLCInventors: Shozo Kawabata, Kenji Shibata, Takaaki Furuyama, Satoru Kawamoto
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Patent number: 7399214Abstract: The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.Type: GrantFiled: May 3, 2006Date of Patent: July 15, 2008Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kunihiko Nishimura, Naoki Yasuda, Yosuke Suzuki, Yoshinobu Hirokado, Satoru Kawamoto