Abstract: A liquid crystal displaying apparatus which is high in displaying quantity is provided, wherein the displaying quantity reduction such as flickering, image sticking, ununiformly displaying and so on which is caused due to changes for each exposing region of the &Dgr;Vgd. In the liquid crystal displaying apparatus of the present invention, a plurality of scanning wirings and a plurality of signal wirings, TFTs and pixel electrodes are formed. Storage capacitance for retaining the electric charge is connected with the pixel electrode, another electrode opposite to an electrode for forming the storage capacitance and the drain electrode of the TFT are formed at the same time, an array substrate where another electrode is superposed on the scanning wiring and the signal wiring through the transparent insulating film, and a liquid crystal displaying provided with an counter substrate having a common electrode to be arranged opposite to the pixel electrode.

Abstract: In an electromagnetic injector control apparatus for an engine, a capacitor is connected to a power supply and a solenoid of an injector for accumulating electric charge at a voltage higher than that of the power supply. A driving circuit controls transistors to supply energy from the power supply to the solenoid during an operation period of the solenoid. The driving circuit also controls a transistor so that a timing to start supplying the accumulated energy from the capacitor to the solenoid is delayed from a timing to start the operation of the solenoid as the voltage of the capacitor increases. Thus, the accumulated energy is used to speed up the operating response of the solenoid. The supply of the accumulated energy to the solenoid is stopped when a current flowing in the solenoid reaches a predetermined cut-off level.

Abstract: A semiconductor memory device that decreases power consumption and increases performance. The semiconductor memory device includes a plurality of memory cells that undergo refreshing to maintain data. The semiconductor memory device includes a normal operation mode for performing normal operation with the memory cells, and a plurality of low power consumption modes for decreasing power consumption when the semiconductor memory device is in a standby state. The semiconductor memory device includes a mode setting circuit that sets one of the low power consumption modes.

Abstract: A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

Abstract: The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

Abstract: The present invention provides a semiconductor memory device that performs a burn-in test. The device includes word lines, pairs of bit lines, memory cells, sense amplifiers connected to the pairs of bit lines for amplifying a potential difference between the associated pair of bit lines, and a burn-in test control circuit for providing a stress voltage to the plurality of word lines and the pairs of bit lines to perform a burn-in test based on the burn-in control signal. The burn-in test control circuit includes a potential difference setting circuit for selecting one of the first word lines so to generate a potential difference between at least one of the pairs of bit lines. The sense amplifiers amplify the potential difference to provide the stress voltage between the word lines and the associated pair of bit lines and between the bit lines of that pair.

Abstract: The first switching circuit selects data of a predetermined bit from the input/output data in accordance with each of a plurality of testing modes and outputs the selected data as testing data. The second switching circuits receive the testing data and each bit of the input/output data, and select one of the input/output data and the testing data in accordance with the operation mode. In detail, each bit of the input/output data is respectively outputted to the memory cells during normal operation mode, and during testing mode the testing data is selected to be outputted to the memory cells as the common input/output data. Thus, write control for multiple kinds of data compressing test can be performed by using the simple first and second switching circuits. As a result, the control circuit for the data compressing test can be reduced in layout size.

Abstract: A semiconductor memory device having a burn-in test capability. The semiconductor memory device includes a detection circuit, which is connected to the plurality of word lines. The detection circuit detects whether a stress voltage for a burn-in test has been applied to all of the word lines along their entire lengths in the burn-in test.

Abstract: A memory device, such as a DRAM, includes multiple cell blocks, each having bit lines and word lines. Block control circuits are connected to respective ones of the cell blocks. The block control circuits supply a precharge signals to their associated cell blocks. A block control circuit which is connected to a defective cell block generates a precharge signal having a precharge level of the bit lines and a reset level of the word lines in accordance with an access condition of the defective cell block. The block control circuit sets the precharge signal to the precharge level when the defective cell block is activated and to the reset level when it is deactivated.

Abstract: A direct sensing type semiconductor memory device combines read and write data bus lines in order to conserve real estate. The memory device includes a bit line pair and a sense amplifier connected between the lines of the bit line pair, and a data line pair. A first transistor is connected between a first potential and one of the data lines of the data line pair, and a gate of the first transistor is connected to one of the bit lines of the bit line pair. A second transistor is connected between the first potential and the other one of the data lines, and its gate is connected to the other of the bit lines. A switch circuit is connected between the data line pair and the bit line pair and transfers data from the data line pair to the bit line pair in accordance with a potential difference between the data line pair and the bit line pair.

Abstract: A compact power supply circuit which can supply power to various apparatuses and circuits with a high degree of stability. A primary constant voltage circuit is connected to a second power supply line, which is supplied with power from a battery only when a relay is closed. The circuit supplies power to a third power supply line at a constant primary voltage. An auxiliary constant voltage circuit is connected to a first power supply line, which is always supplied with power from the battery for supplying power to the third power supply line at a constant auxiliary voltage lower than the primary voltage. A halt control circuit enables the operation of the auxiliary constant voltage circuit if power is supplied to the second power supply line and disables the operation of the auxiliary constant voltage circuit if the supply of power is interrupted for a period equal to or longer than a predetermined allowable time.

Abstract: A matrix liquid crystal display device including at least a TFT array substrate, an opposite substrate arranged opposite to the TFT array substrate, a liquid crystal material interposed between the TFT array substrate and the opposite substrate, TCPs and PCBs; the TFT array substrate including thereon bus lines connected with the TCPs, repair lines, and TFTs; the repair lines being provided on a periphery of the TFT array substrate by means of divisional exposure, wherein the repair lines are provided in such a manner that at least two of the same line patterns are repeated.

Abstract: A matrix liquid crystal display device including at least a TFT array substrate, an opposite substrate arranged opposite to the TFT array substrate, a liquid crystal material interposed between the TFT array substrate and the opposite substrate, TCPs and PCBs; the TFT array substrate including thereon bus lines connected with the TCPs, repair lines, and TFTs; the repair lines being provided on a periphery of the TFT array substrate by means of divisional exposure, wherein the repair lines are provided in such a manner that at least two of the same line patterns are repeated.

Abstract: A semiconductor memory device executes the control of data input/output in accordance with control signals and address signals. The device includes data buses, a memory cell array including a plurality of memory cells, a circuit for selecting a specific memory cell from the memory cells to provide the data buses with cell information data stored in the selected cell and data output control circuit for controlling data output from the memory device, based on at least one control signal provided to the control circuit. The control circuit has an output terminal for outputting the output data, and maintains the terminal at a high-impedance state as long as the cell information provided on the data buses is not supplied to the control circuit.

Abstract: A matrix-addressed type display device has display material sandwiched between two substrates facing each other, and a transparent pixel electrode disposed in matrix arrangement. The display device display characters by the application of a voltage selectively to the transparent pixel electrode by the use of a thin-film transistor. To improve display characteristics, an electric charge capacitor is provided in each pixel. This electric charge capacitor is connected to an adjacent gate electrode path and includes a transparent inner bottom electrode sandwiched between a dielectric substrate and a transparent pixel electrode. A transparent dielectric film is Interposed between the transparent pixel electrode and the transparent inner bottom electrode.

Abstract: A semiconductor memory comprises a memory cell array, a first address bus for transmitting an external address signal, a second address bus for transmitting an internal address signal, an address decoder, and a controller. The address decoder has a decoding portion for decoding an input address signal to select a word line of the memory cell array, and a switching portion for selecting one of the first and second address buses to provide the decoding portion with one of the external and internal address signals. The external and internal address signals can be transferred to the address decoder through the first and second address buses, respectively, according to an address activation signal before an operation mode is determined, thereby shortening the transferring time and decoding time and realizing high-speed memory accessing.

Abstract: The present invention relates to a semiconductor storage device for executing an address multiplex method.

Abstract: An active matrix-type liquid crystal display apparatus, in which a pixel electrode and a common electrode line are not overlapped but coupled capacitively by a floating electrode, so that the pixel electrode and common electrode do not short-circuit, and a storage capacitance is formed by the series connection of a plurality of capacitors. An active matrix-type liquid crystal display apparatus, in which a pixel electrode and a gate electrode line at the succeeding or preceeding row are not overlapped but coupled capacitively by a floating electrode, so that the pixel electrode and gate electrode do not short-circuit, and a storage capacitance is formed by the series connection of a plurality of capacitors.

Abstract: A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a serial data register which includes a number of bit cells corresponding to one word of the memory cell array, a decoder for decoding an address signal and for successively making an access to each bit cell of the serial data register based on a decoded result, a register group comprising m+1 shift registers in correspondence with each digit of the address signal, where each of the shift registers comprise n registers which are connected to form a loop and m and n are integers satisfying m.gtoreq.

Abstract: A high-energy ignition system for an internal combustion engine in which both magnetic and electrical energy stored in an energy storage coil and in a capacitor are supplied to the primary winding of an ignition coil at a predetermined timing. When a first or second switching device is turned off, the capacitor is charged with the energy stored in advance in the energy storage coil, and upon subsequent turning on of the first switching device, energy is stored in the energy storage coil from a DC power supply. At substantially the same time as the turning off of the first switching device at an ignition timing, the second switching device is turned on to supply the primary winding with the energy stored in the energy storage coil and the capacitor. Alternatively, the capacitor is charged with the energy stored in advance in the energy storage coil through the primary winding of the ignition coil and a charging diode at the time of turning off of the second switching device.