Patents by Inventor Satoru Tanigawa

Satoru Tanigawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060114351
    Abstract: A format conversion apparatus for subjecting data having a predetermined resolution to conversion of the resolution according to a resolution of a display screen, comprises: a timing generation unit for generating a timing for thinning out inputted signal data, using a resolution conversion coefficient that is calculated on the basis of a conversion ratio of the resolution; and a selection unit for selecting, from two pieces of input signal data existing before and after the timing generated by the timing generation unit, the signal data that is timewise closer to the timing; wherein resolution conversions in the horizontal direction and the vertical direction are carried out while maintaining the combination of the inputted signals.
    Type: Application
    Filed: November 30, 2005
    Publication date: June 1, 2006
    Inventor: Satoru Tanigawa
  • Patent number: 6999130
    Abstract: A luminance signal/chrominance signal separation apparatus is provided with a detector for detecting diagonal components of a luminance signal from a composite video signal, wide-band pass filters, and narrow-band pass filters, wherein band pass filters to be connected to a three-line chrominance separation circuit are selected according to the amount of diagonal components of the luminance signal, thereby reducing cross color and improving resolution.
    Type: Grant
    Filed: October 11, 2002
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Satoru Tanigawa
  • Patent number: 6903781
    Abstract: A video signal processing apparatus comprises a sub-screen processing integrated circuit for subjecting a sub-screen video signal to scale-down processing to reduce its display region and output the sub-screen video signal, and a main-screen processing integrated circuit comprising: a switching circuit for receiving a main-screen video signal and the scaled-down sub-screen video signal which is outputted from the sub-screen processing integrated circuit, and selecting the main-screen video signal for a main-screen display region while selecting the sub-screen video signal for a sub-screen display region; an A/D conversion circuit for converting the video signal outputted from the switching circuit into a digital video signal; a digital signal processing circuit for digitally processing the digital video signal outputted from the A/D conversion circuit; and a D/A conversion circuit for converting the digitally-processed video signal into an analog video signal.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoru Tanigawa, Atsuhisa Kageyama, Ryuichi Shibutani
  • Publication number: 20050030381
    Abstract: The motion detection device includes an oblique correlation detection section, a motion detection section and a motion determination section. The oblique correlation detection section detects a correlation in an oblique direction (oblique correlation) of a composite video signal. The motion detection section detects a motion amount based on an inter-frame difference of the composite video signal. The motion determination section determines the presence/absence of a motion in the composite video signal based on the motion amount detected by the motion detection section. The motion determination section determines the presence/absence of the motion considering the detection results of the oblique correlation by the oblique correlation detection section.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 10, 2005
    Inventor: Satoru Tanigawa
  • Publication number: 20040212742
    Abstract: A video signal processor and a video signal processing method which can prevent the length of one period of a clock from being shortened and can output a video signal that is in phase with a reference signal. When a video data signal that has been processed using a first clock signal is processed using a second clock signal, this video signal processor does not utilize as the second clock signal, a clock signal that is in phase with a reference signal but a clock signal that is employed in a later stage signal processor, and interpolates the video data signal by an interpolation circuit so as to make the signal in phase with the reference signal.
    Type: Application
    Filed: January 27, 2004
    Publication date: October 28, 2004
    Inventor: Satoru Tanigawa
  • Publication number: 20040109090
    Abstract: An oblique correlation detection section detects correlation in an oblique direction (oblique correlation) of a composite video signal. A line correlation chrominance separation section extracts a first chrominance signal from the composite video signal based on vertical correlation of the composite video signal. A first chrominance signal acquisition section acquires a second chrominance signal based on horizontal self-correlation of the first chrominance signal. The first chrominance signal acquisition section detects the self-correlation within a range corresponding to the degree of the oblique correlation detected by the oblique detection section.
    Type: Application
    Filed: September 24, 2003
    Publication date: June 10, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Satoru Tanigawa
  • Publication number: 20040061530
    Abstract: A clock conversion apparatus includes a memory that can perform writing and reading independently from each other, a first counter circuit for controlling write addresses, a delay adjustment circuit for adjusting a delay time of a reading start reference signal from a writing start reference signal, and a second counter circuit for controlling read addresses from the reading start reference signal, wherein data corresponding to a horizontal sync period are written in the memory over plural times to reduce the capacity of the memory, and a writing start position and a reading start position are delay-adjusted.
    Type: Application
    Filed: August 11, 2003
    Publication date: April 1, 2004
    Inventors: Satoru Tanigawa, Nobutaka Okada
  • Patent number: 6628342
    Abstract: A video signal processing apparatus A comprises: an adder 107 for generating a second address value S106 which has a predetermined phase difference from a first address value S101 outputted by an address value output means 120 and outputting the same; a selector 108 for selecting either a first address value S101 or a second address value S106 to output as an output signal S107; a vertical synchronizing signal output means 123 for outputting the vertical synchronizing signal S104 to the selector 108; a ROM 109 for outputting first data corresponding to the first address value S101 or second data corresponding to the second address value S106 as a signal S108; a loading hold mode flip-flop 110 for preserving the first data; a loading hold mode flip-flop 111 for preserving the second data; and a hue adjustment means B which adjusts the hue of the video signal by using the output signal S109 of the loading hold mode flip-flop 110 and the output signal S110 of the loading hold mode flip-flop 111.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 30, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Satoru Tanigawa
  • Publication number: 20030071921
    Abstract: A luminance signal/chrominance signal separation apparatus is provided with a detector for detecting diagonal components of a luminance signal from a composite video signal, wide-band pass filters, and narrow-band pass filters, wherein band pass filters to be connected to a three-line chrominance separation circuit are selected according to the amount of diagonal components of the luminance signal, thereby reducing cross color and improving resolution.
    Type: Application
    Filed: October 11, 2002
    Publication date: April 17, 2003
    Applicant: MATSUSHITA ELEC IND. CO., LTD.
    Inventor: Satoru Tanigawa
  • Publication number: 20030001969
    Abstract: A video signal processing apparatus comprises a sub-screen processing integrated circuit for subjecting a sub-screen video signal to scale-down processing to reduce its display region and output the sub-screen video signal, and a main-screen processing integrated circuit comprising: a switching circuit for receiving a main-screen video signal and the scaled-down sub-screen video signal which is outputted from the sub-screen processing integrated circuit, and selecting the main-screen video signal for a main-screen display region while selecting the sub-screen video signal for a sub-screen display region; an A/D conversion circuit for converting the video signal outputted from the switching circuit into a digital video signal; a digital signal processing circuit for digitally processing the digital video signal outputted from the A/D conversion circuit; and a D/A conversion circuit for converting the digitally-processed video signal into an analog video signal.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 2, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoru Tanigawa, Atsuhisa Kageyama, Ryuichi Shibutani
  • Publication number: 20010006405
    Abstract: A video signal processing apparatus A comprises: an adder 107 for generating a second address value S106 which has a predetermined phase difference from a first address value S101 outputted by an address value output means 120 and outputting the same; a selector 108 for selecting either a first address value S101 or a second address value S106 to output as an output signal S107; a vertical synchronizing signal output means 123 for outputting the vertical synchronizing signal S104 to the selector 108; a ROM 109 for outputting first data corresponding to the first address value S101 or second data corresponding to the second address value S106 as a signal S108; a loading hold mode flip-flop 110 for preserving the first data; a loading hold mode flip-flop 111 for preserving the second data; and a hue adjustment means B which adjusts the hue of the video signal by using the output signal S109 of the loading hold mode flip-flop 110 and the output signal S110 of the loading hold mode flip-flop 111.
    Type: Application
    Filed: January 4, 2001
    Publication date: July 5, 2001
    Inventor: Satoru Tanigawa