Patents by Inventor Satoru Yamada

Satoru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220251106
    Abstract: An organic compound, represented by formula [1] or [2], suitably used for a thermally activated delayed fluorescent device: where X1 to X18 and X21 to X38 are each independently selected from the group consisting of a hydrogen atom, and substituents, Y is oxygen, sulfur, selenium, tellurium, a CR1R2 group, or a carbonyl group, where R1 and R2 are each independently selected from the group consisting of a hydrogen atom, and substituents, and Z is an alkyl group, an aryl group, or a heterocyclic group.
    Type: Application
    Filed: February 1, 2022
    Publication date: August 11, 2022
    Inventors: Naoki Yamada, Jun Kamatani, Yosuke Nishide, Hirokazu Miyashita, Satoru Shiobara
  • Patent number: 11408318
    Abstract: An exhaust gas purification device is disclosed provided with a denitration catalyst for reducing and removing nitrogen oxides in exhaust gas using ammonia as a reducing agent in a gas flow passage through which the exhaust gas discharged from a boiler flows, and which injects ammonia into the exhaust gas flowing through the gas flow passage on an upstream side of the denitration catalyst, including multiple disturbing plate support members, and a disturbing plate. The multiple disturbing plate support members are fixedly provided on a downstream side of the denitration catalyst and arranged extending linearly in a flow path cross section to cross the gas flow passage. The disturbing plate includes an exhaust gas flow facing surface exposed on an upstream side and is fixed to the disturbing plate support members so that a position thereof in the flow path cross section can be changed.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: August 9, 2022
    Assignee: MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hiroyuki Yoshimura, Katsumi Yano, Katsuhiro Yashiro, Akihiro Yamada, Satoru Shishido, Hironori Kishi
  • Publication number: 20220244673
    Abstract: Provided is an electrophotographic electroconductive member, including: an electroconductive support; an electroconductive layer; and a surface layer in order, wherein an impedance is 1.0×103? to 1.0×108? at an outer surface of the electroconductive member, in the surface layer, an electronic electroconductive agent is dispersed, the electroconductive layer has a matrix containing a cross-linked product of a first rubber and domains each containing a cross-linked product of a second rubber and electroconductive particles, and wherein, and wherein among the domains observed in specified observation regions, 80% by number or more of the domains satisfy (1) and (2): (1) a proportion of sectional areas of the electroconductive particles with respect to the domain is 20% or more; (2) A/B is 1.00 to 1.10 when A is a perimeter of the domain and B is an envelope perimeter.
    Type: Application
    Filed: April 11, 2022
    Publication date: August 4, 2022
    Inventors: Kenji Takashima, Kazuhiro Yamauchi, Satoru Nishioka, Yuichi Kikuchi, Takumi Furukawa, Masaki Yamada
  • Publication number: 20220238813
    Abstract: An organic light-emitting element including a first electrode, a second electrode, and a light-emitting layer located between the first electrode and the second electrode. The light-emitting layer contains a first organic compound material, a second organic compound that is a delayed fluorescent material, and a third organic compound that is a light-emitting material. In the second organic compound, an electron is transferred from a plurality of occupied molecular orbitals (OMO) to a lowest unoccupied molecular orbital (LUMO) in a second excited triplet state.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 28, 2022
    Inventors: Satoru Shiobara, Naoki Yamada, Hirokazu Miyashita, Yosuke Nishide, Jun Kamatani, Hiroki Ohrui
  • Publication number: 20220223713
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 14, 2022
    Inventors: Naoto Umezawa, Satoru Yamada, Junsoo Kim, Honglae Park, Chunhyung Chung
  • Patent number: 11355509
    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Inventors: Kiseok Lee, Junsoo Kim, Hui-Jung Kim, Bong-Soo Kim, Satoru Yamada, Kyupil Lee, Sunghee Han, Hyeongsun Hong, Yoosang Hwang
  • Patent number: 11342436
    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaeho Hong, Yongseok Kim, Hyuncheol Kim, Seokhan Park, Satoru Yamada, Kyunghwan Lee
  • Patent number: 11329137
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: May 10, 2022
    Inventors: Naoto Umezawa, Satoru Yamada, Junsoo Kim, Honglae Park, Chunhyung Chung
  • Patent number: 11322544
    Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwan Lee, Yongseok Kim, Taehun Kim, Seokhan Park, Satoru Yamada, Jaeho Hong
  • Patent number: 11289262
    Abstract: An electronic component includes; a magnetic-body core having a plate-shaped portion and a core portion which extends from an upper surface of the plate-shaped portion; a winding wire which includes a wound portion wound by a rectangular wire into an Edgewise winding form and two non-wound portions extending from the wound portion to two distal ends, and the core portion is inserted through the wound portion; and a magnetic exterior body which covers at least the wound portion and the core portion. The two non-wound portions are respectively arranged along a bottom surface and at least one of the side surfaces of the plate-shaped portion. Parts of the two non-wound portions arranged along the bottom surface are electrodes.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: March 29, 2022
    Inventors: Mitsugu Kawarai, Satoru Yamada, Kazuyuki Kikuchi, Tomohiro Kajiyama, Juichi Ooki, Motomi Takahashi, Tsutomu Otsuka
  • Publication number: 20220052257
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
    Type: Application
    Filed: October 29, 2021
    Publication date: February 17, 2022
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
  • Publication number: 20210376099
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
    Type: Application
    Filed: August 12, 2021
    Publication date: December 2, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Eunae Cho, Dongjin Lee, Ji Eun Lee, Kyoung-Ho Jung, Dong Su Ko, Yongsu Kim, Jiho Yoo, Sung Heo, Hyun Park, Satoru Yamada, Moonyoung Jeong, Sungjin Kim, Gyeongsu Park, Han Jin Lim
  • Publication number: 20210358913
    Abstract: A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer.
    Type: Application
    Filed: November 9, 2020
    Publication date: November 18, 2021
    Inventors: Hyuncheol KIM, Yongseok KIM, Huijung KIM, Satoru YAMADA, Sungwon YOO, Kyunghwan LEE, Jaeho HONG
  • Patent number: 11165018
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Seok Han Park, Satoru Yamada, Jae Ho Hong
  • Publication number: 20210335798
    Abstract: Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.
    Type: Application
    Filed: April 12, 2021
    Publication date: October 28, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Hyun Cheol KIM, Satoru YAMADA, Sung Won YOO, Jae Ho HONG
  • Publication number: 20210319293
    Abstract: A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.
    Type: Application
    Filed: April 7, 2021
    Publication date: October 14, 2021
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Hyun Cheol KIM, Satoru YAMADA, Sung Won YOO, Jae Ho HONG
  • Patent number: 11127828
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 21, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunae Cho, Dongjin Lee, Ji Eun Lee, Kyoung-Ho Jung, Dong Su Ko, Yongsu Kim, Jiho Yoo, Sung Heo, Hyun Park, Satoru Yamada, Moonyoung Jeong, Sungjin Kim, Gyeongsu Park, Han Jin Lim
  • Publication number: 20210249417
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Publication number: 20210225842
    Abstract: A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.
    Type: Application
    Filed: August 21, 2020
    Publication date: July 22, 2021
    Inventors: Hyuncheol KIM, Yongseok KIM, Satoru YAMADA, Sungwon YOO, Kyunghwan LEE, Jaeho HONG
  • Patent number: 11046803
    Abstract: The present invention addresses the problem of providing a block copolymer which is useful as a surface treatment agent for cell culture substrates, said surface treatment agent enabling cell separation in a short period of time. The above-mentioned problem is solved by a block copolymer that includes the following blocks (A), (B) and (C): (A) a temperature-responsive polymer block that has a lower critical solution temperature (LCST) within the range of from 0° C. to 50° C. with respect to water (B) a hydrophilic polymer block that does not have an LCST within the range of from 0° C. to 50° C., while having an HLB value within the range of from 9 (inclusive) to 20 (exclusive) (C) a hydrophobic polymer block that does not have an LCST within the range of from 0° C. to 50° C., while having an HLB value within the range of from 0 (inclusive) to 9 (exclusive).
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 29, 2021
    Assignee: TOSOH CORPORATION
    Inventors: Yukie Maejima, Satoru Kondou, Shinya Imatomi, Satoru Yamada, Hiroyuki Ito