Patents by Inventor Satoru Yamada

Satoru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210151101
    Abstract: A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.
    Type: Application
    Filed: September 29, 2020
    Publication date: May 20, 2021
    Inventors: KYUNGHWAN LEE, YONGSEOK KIM, CHEONAN LEE, SATORU YAMADA, JUNHEE LIM
  • Patent number: 11011299
    Abstract: A terminal plate member on which a terminal of a coil component is mounted including: an annular frame having an inner peripheral edge; a pair of extension members extending from the inner peripheral edge of the annular frame toward an inner space of the annular frame member in a first direction; and a deformable section provided in the annular frame at proximal end of one of the pair of extension members, the deformable section having a more easily deformable property than other sections of the annular frame when force is applied. The deformable section is provided along at least an entire width in a second direction of the one of the pair of extension members. The second direction is perpendicular to the first direction.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 18, 2021
    Inventors: Yoshiyuki Tahara, Teruaki Tanaka, Akihiko Nakamura, Satoru Yamada, Mitsugu Kawarai
  • Publication number: 20210143335
    Abstract: An organic compound represented by formula [1]. The compounds are of the class of diacenaphthochrysene compound, useful as organic light emitting device. In the formula [1], R1 to R18 are each independently selected from the group consisting of a hydrogen atom and a substituent.
    Type: Application
    Filed: October 29, 2020
    Publication date: May 13, 2021
    Inventors: Yosuke Nishide, Hirokazu Miyashita, Satoru Shiobara, Hiroki Ohrui, Naoki Yamada, Jun Kamatani
  • Publication number: 20210139417
    Abstract: An organic compound represented by formula [1]. In the formula rings Q represented by formula [1-1] are each independently present at positions *1 and *2 such that positions * of the rings Q correspond to the positions *1 and *2. The rings Q may be the same or different. R4 and R5 represent groups each independently selected from the group consisting of a hydrogen atom and a substituted or unsubstituted aryl group. The rings Q are aromatic hydrocarbons. R1 to R3 represent groups each independently selected from the group consisting of a hydrogen atom, a substituted or unsubstituted alkyl group, a substituted or unsubstituted aryl group, and a cyano group. At least one of R1 to R3 represents a cyano group.
    Type: Application
    Filed: September 2, 2020
    Publication date: May 13, 2021
    Inventors: Hiroki Ohrui, Hirokazu Miyashita, Satoru Shiobara, Yosuke Nishide, Naoki Yamada, Jun Kamatani
  • Publication number: 20210134975
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.
    Type: Application
    Filed: July 13, 2020
    Publication date: May 6, 2021
    Inventors: Naoto Umezawa, Satoru Yamada, Junsoo Kim, Honglae Park, Chunhyung Chung
  • Patent number: 10996581
    Abstract: Provided is such a conductive member that a change in its electrical resistance value caused by its long-term use is reduced to the extent possible. The conductive member has a conductive support and a conductive layer, the conductive layer contains a rubber composition formed of a modified epichlorohydrin rubber, and the modified epichlorohydrin rubber has a unit represented by the following formula (1). In the formula (1), R1, R2, and R3 each independently represent hydrogen or a saturated hydrocarbon group having 1 to 18 carbon atoms.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 4, 2021
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Norifumi Muranaka, Satoru Yamada, Kazuhiro Yamauchi, Seiji Tsuru, Yuka Muranaka
  • Publication number: 20210126214
    Abstract: An organic EL device includes at least an anode, a first light-emitting layer, an intermediate layer, a second light-emitting layer, and a cathode in this order. The intermediate layer is adjacent to the first light-emitting layer and the second light-emitting layer. The first light-emitting layer and the second light-emitting layer can trap electrons. A material constituting the intermediate layer is a hydrocarbon that has a HOMO level equal to or lower than the HOMO level of a host of the first light-emitting layer and that has a high S1 level.
    Type: Application
    Filed: December 31, 2020
    Publication date: April 29, 2021
    Inventors: Hirokazu Miyashita, Itaru Takaya, Takayuki Ito, Moe Takahira, Tomona Yamaguchi, Satoru Shiobara, Tomokazu Kotake, Haruna Iida, Naoki Yamada, Jun Kamatani
  • Patent number: 10991699
    Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: April 27, 2021
    Inventors: Hui-Jung Kim, Min Hee Cho, Bong-Soo Kim, Junsoo Kim, Satoru Yamada, Wonsok Lee, Yoosang Hwang
  • Publication number: 20210084736
    Abstract: An apparatus, system, and method of remotely monitoring receives, from an operation terminal, identification information and location information of a location of one or more lamps, stores, in a memory, the received identification information and the received location information in association with each other for the one or more lamps, updates log information regarding a log of a lighting condition of the one or more lamps, in response to an indication that an electric circuit of the one or more lamps is energized for the one or more lamps, and sends monitoring information corresponding to the log information of the electric circuit of the one or more lamps for display.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventor: Satoru YAMADA
  • Publication number: 20210074914
    Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.
    Type: Application
    Filed: October 3, 2019
    Publication date: March 11, 2021
    Inventors: Kyung Hwan LEE, Yong Seok KIM, Tae Hun KIM, Seok Han PARK, Satoru YAMADA, Jae Ho HONG
  • Patent number: 10930740
    Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hae-in Jung, Moon-young Jeong, Joon Han, Satoru Yamada
  • Patent number: 10916543
    Abstract: A semiconductor device includes first and second active regions extending in a first direction on a substrate and spaced apart from each other in a second direction intersecting the first direction, wherein the first and second active regions overlaps with each other in the second direction, a third active region extending in the first direction on the substrate and spaced apart from the first active region in the second direction. The first active region is positioned between the second and third active regions in the second direction. The first and third active regions partially overlap in the second direction, and a device isolation film is configured to define the first to third active regions.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Uk Han, Taek Yong Kim, Satoru Yamada, Jun Hee Lim, Ki Jae Hur
  • Publication number: 20210036020
    Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 4, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seok Han PARK, Yong Seok KIM, Hui-Jung KIM, Satoru YAMADA, Kyung Hwan LEE, Jae Ho HONG, Yoo Sang HWANG
  • Patent number: 10904991
    Abstract: An apparatus, system, and method of remotely monitoring receives, from an operation terminal, identification information and location information of a location of one or more lamps, stores, in a memory, the received identification information and the received location information in association with each other for the one or more lamps, updates log information regarding a log of a lighting condition of the one or more lamps, in response to an indication that an electric circuit of the one or more lamps is energized for the one or more lamps, and sends monitoring information corresponding to the log information of the electric circuit of the one or more lamps for display.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: January 26, 2021
    Assignee: Ricoh Company, Ltd.
    Inventor: Satoru Yamada
  • Patent number: 10886280
    Abstract: Provided are a semiconductor device having a gate and a method of forming the same. The method includes forming a gate dielectric, forming a first conductive material layer on the gate dielectric, forming a source material layer on the first conductive material layer, and diffusing a first element included in the source material layer into the first conductive material layer by performing a thermal treatment process to form a doped material layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongjin Lee, Ji-Eun Lee, Kyoung-Ho Jung, Satoru Yamada, Moonyoung Jeong
  • Patent number: 10886375
    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: January 5, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongjin Lee, Junsoo Kim, Moonyoung Jeong, Satoru Yamada, Dongsoo Woo, Jiyoung Kim
  • Publication number: 20200403079
    Abstract: A semiconductor device includes a substrate including a recess, a first gate insulation layer on a lower sidewall and a bottom of the recess, the first gate insulation layer including an insulation material having hysteresis characteristics, a first gate electrode on the first gate insulation layer inside the recess, a second gate electrode contacting the first gate electrode in the recess, the second gate electrode including a material different from a material of the first gate electrode, and impurity regions on the substrate and adjacent to sidewalls of the recess, bottoms of the impurity regions being higher than a bottom of the second gate electrode relative to a bottom of the substrate.
    Type: Application
    Filed: February 26, 2020
    Publication date: December 24, 2020
    Inventors: Jaeho HONG, Yongseok KIM, Hyuncheol KIM, Seokhan PARK, Satoru YAMADA, Kyunghwan LEE
  • Publication number: 20200395412
    Abstract: A vertical semiconductor device includes: a channel on a substrate, the channel extending in a first direction substantially perpendicular to an upper surface of the substrate; a first data storage structure contacting a first sidewall of the channel; a second data storage structure on a second sidewall of the channel; and gate patterns on a surface of the second data storage structure, wherein the gate patterns are spaced apart from each other in the first direction, and the gate patterns extend in a second direction substantially parallel to the upper surface of the substrate.
    Type: Application
    Filed: January 6, 2020
    Publication date: December 17, 2020
    Inventors: Kyunghwan LEE, Yongseok KIM, Taehun KIM, Seokhan PARK, Satoru YAMADA, Jaeho HONG
  • Publication number: 20200388625
    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Kiseok Lee, Junsoo Kim, Hui-Jung Kim, Bong-Soo Kim, Satoru Yamada, Kyupil Lee, Sunghee Han, HyeongSun Hong, Yoosang Hwang
  • Publication number: 20200303504
    Abstract: Provided are a multi-direction channel transistor having a gate having an increased effective width and a multi-direction channel, and a semiconductor device including the multi-direction channel transistor, wherein the multi-direction channel transistor includes at least one fin on an active region on a substrate and disposed adjacent to a recess extending in a first direction; a gate line extending in a second direction crossing the first direction and covering at least a portion of the at least one fin and the recess; source/drain regions on the active region at both sides of the gate line; and a channel region in the active region under the gate line between the source/drain regions, wherein the first direction is diagonal to the second direction, and a dielectric film under the gate line has substantially the same thickness on both the at least one fin and the recess.
    Type: Application
    Filed: August 21, 2019
    Publication date: September 24, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hae-in JUNG, Moon-young JEONG, Joon HAN, Satoru YAMADA