Patents by Inventor Satoru Yamada

Satoru Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190312119
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
    Type: Application
    Filed: June 5, 2019
    Publication date: October 10, 2019
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunae CHO, Dongjin Lee, Ji Eun Lee, Kyoung-Ho Jung, Dong Su Ko, Yongsu Kim, Jiho Yoo, Sung Heo, Hyun Park, Satoru Yamada, Moonyoung Jeong, Sungjin Kim, Gyeongsu Park, Han Jin Lim
  • Publication number: 20190304660
    Abstract: A coil component including a coil formed by winding an insulation-coated wire and a composite magnetic body embed with the coil, wherein the composite magnetic body contains: a metallic magnetic powder made by powderizing a metallic magnetic material and a binder resin; and wherein the average particle size D50[?m] of the metallic magnetic powder satisfies the following formula (1): D50?2.192×(Fmax)?0.518×?0.577??(1) wherein (Fmax) is an upper limit operation-frequency [MHz] at which Q-value starts decreasing beyond the maximum value in a case of increasing the frequency applied to the coil component, and “?” is electrical-resistivity [??·cm] of the metallic magnetic material.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 3, 2019
    Inventors: Mitsugu KAWARAI, Satoru YAMADA
  • Patent number: 10431680
    Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 1, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungsam Lee, Junsoo Kim, Hyoshin Ahn, Satoru Yamada, Joohyun Jeon, MoonYoung Jeong, Chunhyung Chung, Min Hee Cho, Kyo-Suk Chae, Eunae Choi
  • Patent number: 10429782
    Abstract: A fixing device includes a cylindrical film a pressing member, and a preventing member including a preventing surface configured to prevent movement of the film in a longitudinal direction, and a film rotation guiding surface. As viewed in the longitudinal direction of the film, the preventing surface includes first and second regions positioned downstream and upstream, respectively, of a nip center line with respect to a recording material feeding direction. The first region retracts from a longitudinal film end surface relative to the second region. The second region continuously extends in the recording material feeding direction from a portion upstream of the nip center line to a portion downstream of the nip center line, and has a length, with respect to a rotational direction of the film, that is greater at the portion upstream of the nip center line than at the portion downstream of the nip center line.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 1, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Honke, Satoru Taniguchi, Masaki Hirose, Taisuke Minagawa, Keita Nakajima, Kazushi Nishikata, Fumiki Inui, Koichi Yamada
  • Publication number: 20190296017
    Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.
    Type: Application
    Filed: June 11, 2019
    Publication date: September 26, 2019
    Inventors: MIN HEE CHO, JUN SOO KIM, HUI JUNG KIM, TAE YOON AN, SATORU YAMADA, WON SOK LEE, NAM HO JEON, MOON YOUNG JEONG, KI JAE HUR, JAE HO HONG
  • Publication number: 20190267545
    Abstract: The present disclosure provides a photoelectric conversion element including a lower electrode, a photoelectric conversion layer, and an upper electrode in this order, wherein the photoelectric conversion layer includes a first organic compound and a second organic compound having a lower reduction potential than that of the first organic compound, the first organic compound has an emission lifetime of 1.1 ns or more in chloroform solution, and the first organic compound is an organic compound represented by Formula [1] according to claim 1, a fluoranthene derivative, or a metal complex.
    Type: Application
    Filed: May 7, 2019
    Publication date: August 29, 2019
    Inventors: Tomona Yamaguchi, Naoki Yamada, Tetsuo Takahashi, Jun Kamatani, Yosuke Nishide, Hirokazu Miyashita, Satoru Shiobara, Hironobu Iwawaki, Hiroki Ohrui, Masumi Itabashi
  • Publication number: 20190267411
    Abstract: A photoelectric conversion element including an anode, a cathode, and a photoelectric conversion layer, wherein the photoelectric conversion layer contains a first organic compound and a second organic compound, and difference between oxidation potential of first organic compound and reduction potential of second organic compound is larger than 1.5 [V], and the first organic compound is any one of general formulae [1] below, a fluoranthene derivative, and a metal complex, R1 represents a hydrogen atom or a substituent, Ar1, Ar2, and Z1 represents a substituent, n1 and n2 represents an integer of 0 to 4, and X1 to X3 represents a nitrogen atom, a sulfur atom, an oxygen atom, or a carbon atom.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventors: Satoru Shiobara, Naoki Yamada, Tetsuo Takahashi, Jun Kamatani, Yosuke Nishide, Hirokazu Miyashita, Tomona Yamaguchi, Hironobu Iwawaki, Hiroki Ohrui, Norifumi Kajimoto, Masumi Itabashi, Kentaro Ito
  • Patent number: 10361205
    Abstract: A semiconductor device and a method for fabricating the same are provided. A semiconductor device having a substrate can include a lower semiconductor layer, an upper semiconductor layer on the lower semiconductor layer, and a buried insulating layer between the lower semiconductor layer and the upper semiconductor layer. A first trench can be in the upper semiconductor layer having a lowest surface above the buried insulating layer and a first conductive pattern recessed in the first trench. A second trench can be in the lower semiconductor layer, the buried insulating layer, and the upper semiconductor layer. A second conductive pattern can be in the second trench and a first source/drain region can be in the upper semiconductor layer between the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Jun Soo Kim, Hui Jung Kim, Tae Yoon An, Satoru Yamada, Won Sok Lee, Nam Ho Jeon, Moon Young Jeong, Ki Jae Hur, Jae Ho Hong
  • Publication number: 20190194376
    Abstract: The present invention addresses the problem of providing a block copolymer which is useful as a surface treatment agent for cell culture substrates, said surface treatment agent enabling cell separation in a short period of time. The above-mentioned problem is solved by a block copolymer that includes the following blocks (A), (B) and (C):(A) a temperature-responsive polymer block that has a lower critical solution temperature (LCST) within the range of from 0° C. to 50° C. with respect to water (B) a hydrophilic polymer block that does not have an LCST within the range of from 0° C. to 50° C., while having an HLB value within the range of from 9 (inclusive) to 20 (exclusive) (C) a hydrophobic polymer block that does not have an LCST within the range of from 0° C. to 50° C., while having an HLB value within the range of from 0 (inclusive) to 9 (exclusive).
    Type: Application
    Filed: July 28, 2017
    Publication date: June 27, 2019
    Applicant: TOSOH CORPORATION
    Inventors: Yukie MAEJIMA, Satoru KONDOU, Shinya IMATOMI, Satoru YAMADA, Hiroyuki ITO
  • Publication number: 20190196388
    Abstract: A fixing apparatus includes: a fixing member including a heater as a heat source; and a hardware processor that uses pulse width modulation (PWM) control to control power supplied to the heater; wherein the hardware processor changes a duty of the PWM control within a half cycle of an input current of the PWM control.
    Type: Application
    Filed: November 16, 2018
    Publication date: June 27, 2019
    Applicant: KONICA MINOLTA, INC.
    Inventors: Yukinobu Iguchi, Satoru Sasaki, Yoshihito Sasamoto, Naoto Sugaya, Kenichi Hayashi, Yohei Yamada
  • Publication number: 20190198626
    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
    Type: Application
    Filed: February 28, 2019
    Publication date: June 27, 2019
    Inventors: Dongjin LEE, Junsoo KIM, Moonyoung JEONG, Satoru YAMADA, Dongsoo WOO, Jiyoung KIM
  • Patent number: 10325992
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunae Cho, Dongjin Lee, Ji Eun Lee, Kyoung-Ho Jung, Dong Su Ko, Yongsu Kim, Jiho Yoo, Sung Heo, Hyun Park, Satoru Yamada, Moonyoung Jeong, Sungjin Kim, Gyeongsu Park, Han Jin Lim
  • Publication number: 20190164985
    Abstract: A semiconductor memory device comprises a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also comprises a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer comprises semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.
    Type: Application
    Filed: July 5, 2018
    Publication date: May 30, 2019
    Inventors: Kiseok LEE, Junsoo KIM, Hui-Jung KIM, Bong-Soo KIM, Satoru YAMADA, Kyupil LEE, Sunghee HAN, HyeongSun HONG, Yoosang HWANG
  • Patent number: 10305071
    Abstract: A nonaqueous electrolyte battery and a battery package are provided. The nonaqueous electrolyte battery includes a battery element; a nonaqueous electrolyte; and a battery package configured to accommodate the battery element, wherein the battery package includes a first layer; a second layer including a carbon material; and a metal layer, wherein the second layer is directly provided on the metal layer.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: May 28, 2019
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroshi Seino, Hideaki Ojima, Fumihata Yamamoto, Hiroyuki Yamada, Satoru Tanaka, Ryoko Sato, Ryuji Soeda
  • Patent number: 10295917
    Abstract: Provided is an electrophotographic roller including a cylindrical base and an elastic layer on an outer peripheral surface of the base, the base having a joint extending from one end to the other end in a longitudinal direction thereof, at least a part of the joint has a gap penetrating the joint in a thickness direction of the base, and a part of a material for the elastic layer entering the gap and covering a portion of an inner peripheral surface of the base near the gap to form an anchor portion of the elastic layer.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: May 21, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiro Suzuki, Satoru Yamada
  • Publication number: 20190148644
    Abstract: The present disclosure provides an organic compound expressed by the following General Formula 1: In General Formula 1, a partial structure Z1 represents a condensed polycyclic group that may include a nitrogen atom in a skeleton, and that includes at least one of a five-membered ring and a six-membered ring. The partial structure Z1 may include, as a substituent, a carbonyl group, a dicyanovinylidene group, a halogen atom, a cyano group, an alkyl group, an alkoxy group, an aromatic heterocyclic group, or an aryl group. R1 and R2 represent an alkyl group, aryl group, an aromatic heterocyclic group, a halogen group, or a cyano group. Ar1 represents an arylene group or a divalent aromatic heterocyclic group, and Ar2 and Ar3 represent an aryl group or an aromatic heterocyclic group. n represents an integer of 1 to 4.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Inventors: Naoki Yamada, Jun Kamatani, Hiroki Ohrui, Hironobu Iwawaki, Masumi Itabashi, Yosuke Nishide, Hirokazu Miyashita, Satoru Shiobara, Tomona Yamaguchi, Tetsuo Takahashi
  • Publication number: 20190137874
    Abstract: Provided is a photosensitive composition including: a polymer (P) which includes a structural unit derived from a vinylbenzene derivative, a structural unit including a radical polymerizable group, and a structural unit including at least one kind of functional group selected from the group consisting of a primary hydroxyl group and an amino group, and in which the content of the structural unit derived from the vinylbenzene derivative is equal to or greater than 30% by mol; and a radical polymerization initiator.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 9, 2019
    Applicant: FUJIFILM Corporation
    Inventors: Takashi ARIDOMI, Shinichi Kanna, Satoru Yamada
  • Patent number: 10280148
    Abstract: Provided is an electroconductive member for electrophotography in which movement of a quaternary ammonium salt toward the surface of a binder resin is suppressed and which exhibits a less reduction in electroconductivity through electrification. The electroconductive member for electrophotography comprises an electroconductive shaft core and a resin layer, and the resin layer comprises a binder resin and at least one selected from quaternary ammonium salts having structures represented by the formulae (1) to (8).
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: May 7, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Satoru Nishioka, Satoru Yamada, Kazuhiro Yamauchi, Yuichi Kikuchi
  • Patent number: 10263084
    Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: April 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongjin Lee, Junsoo Kim, Moonyoung Jeong, Satoru Yamada, Dongsoo Woo, Jiyoung Kim
  • Patent number: D861043
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 24, 2019
    Assignee: YAMADA CORPORATION
    Inventors: Satoru Suwabe, Kotaro Yamada