Patents by Inventor Satoshi Hibino

Satoshi Hibino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080138509
    Abstract: A magnetic sensor comprises a spin-valve type magnetoresistive element arranged on a substrate, wherein a bias magnetic layer made of a permanent magnet film is connected with both ends of the magnetoresistive element so as to detect the magnitude of a magnetic field. The bias magnetic layer is formed on an embedded layer made of a non-magnetic material, which comprises a thick first layer and a thin second layer that are sequentially formed and laminated together. The bias magnetic layer is composed of a CoCrPt alloy, and the thickness thereof ranges from 800 ? to 900 ?; the embedded layer is composed of Cr or a Cr alloy; the thickness of the first layer ranges from 2 nm to 10 nm. Thus, it is possible to freely set the combination of the coercive force and residual magnetism in the bias magnetic layer without changing the composition of a target.
    Type: Application
    Filed: July 25, 2007
    Publication date: June 12, 2008
    Applicant: YAMAHA CORPORATION
    Inventor: Satoshi Hibino
  • Publication number: 20070037782
    Abstract: Provided is a medicament having an excellent therapeutic effect on ageing macular degeneration. The therapeutic agent for ageing macular degeneration comprises a progesterone derivative represented by the following formula (1): (wherein, R1 represents an alkyl group having from 1 to 23 carbon atoms) as an effective ingredient.
    Type: Application
    Filed: March 23, 2004
    Publication date: February 15, 2007
    Applicant: MEIJI DAIRIES CORPORATION
    Inventors: Satoshi Hibino, Masashi Yamada, Taketo Yamaji, Hiroto Suzuki
  • Patent number: 7075121
    Abstract: A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and having a stoichiometric composition; and an upper conductive layer formed on the second oxide layer, wherein the first oxide layer is oxidized during a process of forming the second oxide layer and has an oxygen concentration which is lower than an oxygen concentration of the second oxide layer and lowers with a depth in the first oxide layer, and the first and second oxide layers form a tunneling barrier.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: July 11, 2006
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Publication number: 20050063106
    Abstract: A magnetic sensor comprises a spin-valve type magnetoresistive element arranged on a substrate, wherein a bias magnetic layer made of a permanent magnet film is connected with both ends of the magnetoresistive element so as to detect the magnitude of a magnetic field. The bias magnetic layer is formed on an embedded layer made of a non-magnetic material, which comprises a thick first layer and a thin second layer that are sequentially formed and laminated together. The bias magnetic layer is composed of a CoCrPt alloy, and the thickness thereof ranges from 800 ? to 900 ?; the embedded layer is composed of Cr or a Cr alloy; the thickness of the first layer ranges from 2 nm to 10 nm. Thus, it is possible to freely set the combination of the coercive force and residual magnetism in the bias magnetic layer without changing the composition of a target.
    Type: Application
    Filed: September 9, 2004
    Publication date: March 24, 2005
    Inventor: Satoshi Hibino
  • Publication number: 20040183091
    Abstract: A tunneling junction element comprises: a substrate; a lower conductive layer formed on the substrate; a first oxide layer formed on the lower conductive layer and having a non-stoichiometric composition;a second oxide layer formed on the first oxide layer and having a stoichiometric composition; and an upper conductive layer formed on the second oxide layer, wherein the first oxide layer is oxidized during a process of forming the second oxide layer and has an oxygen concentration which is lower than an oxygen concentration of the second oxide layer and lowers with a depth in the first oxide layer, and the first and second oxide layers form a tunneling barrier.
    Type: Application
    Filed: March 31, 2004
    Publication date: September 23, 2004
    Inventor: Satoshi Hibino
  • Patent number: 6764960
    Abstract: An aluminium film is formed by sputtering on a ferromagnetic layer made of, e.g., Ni—Fe alloy. The aluminum film is oxidized while an alumina film is deposited on the aluminum film by reactive sputtering, to form a tunneling barrier film. Assuming that the aluminum film has a thickness of 1 nm and the alumina film deposited has a thickness of 0.2 nm, an alumina film having a thickness of about 1.5 nm is formed on the ferromagnetic layer, this alumina film being a lamination of an alumina film which is the oxidized aluminum film and the deposited alumina film. The surface of the ferromagnetic layer is prevented from being oxidized because of the presence of the aluminum film. A thin oxide film such as alumina can be formed in a short time without oxidizing an underlying layer.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: July 20, 2004
    Assignee: Yamaha Corp.
    Inventor: Satoshi Hibino
  • Publication number: 20020076940
    Abstract: An aluminium film is formed by sputtering on a ferromagnetic layer made of, e.g., Ni—Fe alloy. The aluminum film is oxidized while an alumina film is deposited on the aluminum film by reactive sputtering, to form a tunneling barrier film. Assuming that the aluminum film has a thickness of 1 nm and the alumina film deposited has a thickness of 0.2 nm, an alumina film having a thickness of about 1.5 nm is formed on the ferromagnetic layer, this alumina film being a lamination of an alumina film which is the oxidized aluminum film and the deposited alumina film. The surface of the ferromagnetic layer is prevented from being oxidized because of the presence of the aluminum film. A thin oxide film such as alumina can be formed in a short time without oxidizing an underlying layer.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 20, 2002
    Applicant: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 6375687
    Abstract: An apparatus for manufacturing a semiconductor device including the steps of: preparing a substrate having an insulating layer with a connection hole; forming a wiring layer covering the connection hole; and heating the substrate to a temperature equal to or higher than a temperature of fluidizing the wiring layer material and rotating the substrate in a direction of generating centrifugal force directing from an opening of the connection hole toward the bottom of the connection hole.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: April 23, 2002
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 6150250
    Abstract: An electrode material layer of a WSi.sub.2 /polysilicon lamination layer and a conductive material layer for antireflection made of TiN or TiON and containing the direction <200> are sequentially deposited on a gate insulating film. The conductive material layer is patterned through dry etching using a resist layer as a mask to leave a portion of the conductive material layer. The resist layer may be as thin as capable of patterning the conductive material layer. After the resist layer is removed, the electrode material layer is patterned through dry etching using the conductive material layer as a mask to leave a portion of the electrode material layer. A lamination of the left electrode material layer and conductive material layer is used as a gate electrode layer. A lamination of the resist layer and conductive material layer may be used as a mask.
    Type: Grant
    Filed: November 5, 1998
    Date of Patent: November 21, 2000
    Assignee: Yamaha Corporation
    Inventors: Suguru Tabara, Satoshi Hibino
  • Patent number: 6130158
    Abstract: A method of manufacturing a semiconductor device includes the steps of: preparing a substrate having an insulating layer with a connection hole; forming a wiring layer covering the connection hole; and heating the substrate to a temperature equal to or higher than a temperature of fluidizing the wiring layer material and rotating the substrate in a direction of generating centrifugal force directing from an opening of the connection hole toward the bottom of the connection hole. The centrifugal force facilitates reflow of the wiring layer so that the inside of the connection hole can be more preferably filled and the surface of the wiring layer can be planarized.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: October 10, 2000
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 6033923
    Abstract: After a TiN film is formed on an Si substrate by sputtering, CVD or the like, an optical constant such as a refractive index of the TiN film is measured. If the refractive index relative to light having a wavelength of 700 nm is 2.0 or smaller, it is judged that a nitridation degree of the TiN film is sufficiently high (near to a composition ratio Ti/N=1). A W film formed on the TiN film judged as above has good adhesion relative to the TiN film. This W film forming method may be applied to forming a wiring with a W plug.
    Type: Grant
    Filed: October 8, 1997
    Date of Patent: March 7, 2000
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 6022142
    Abstract: A method of measuring a substrate temperature includes the steps of: forming a first lamination of different metals on a substrate; subjecting the substrate to a heat treatment; measuring a sheet resistance of the substrate after the heat treatment; and estimating a temperature of the substrate during the heat treatment from a correlation between sheet resistances and heat treatment temperatures, the correlation being prepared in advance by subjecting preparatory substrates each having a second lamination having the same structure as the first lamination to heat treatments at a plurality of predetermined heat treatment temperatures and by measuring the sheet resistance of each second lamination layer after the heat treatment. The substrate temperature during heat treatment can be estimated easily without intervening the actual manufacture process by a temperature measuring process.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: February 8, 2000
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 5894222
    Abstract: A method of testing the electrical capacity of a plurality of secondary batteries connected to a load. The battery testing method reduces the time during which the entire electrical capacity of the secondary batteries remains low. In the case of secondary batteries which are made up of a nickel cadmium battery cell, the testing method prevents a memory effect from arising in the batteries. Using the battery testing method, the secondary battery is forcibly discharged, whereby the characteristics of the battery resulting from the discharge are tested. During the test, the secondary battery to be tested is discharged when the other secondary batteries are charged to saturation. In the case of the nickel cadmium secondary batteries, the batteries are fully discharged. The electrical capacity of the secondary battery is checked by measuring the time that elapses before the secondary battery has completely discharged.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: April 13, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventor: Satoshi Hibino
  • Patent number: 5801399
    Abstract: A stress relaxation layer is inserted between an electrode layer and an antireflection layer to relax a stress imparted from one of the electrode and antireflection layers to the other. A semiconductor device is provided which can suppress separation of the antireflection film during device fabrication processes and dispense with the process of etching and removing the antireflection film.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: September 1, 1998
    Assignee: Yamaha Corporation
    Inventors: Atsuo Hattori, Satoshi Hibino
  • Patent number: 5776827
    Abstract: An insulating layer 6 is formed covering a lower level wiring layer 5. Contact hole 11 registered with the lower level wiring 5 is then formed in the insulating layer 6. An adhesion layer 12 is sputtered on the lower level wiring layer 5 and a whole surface of the third level insulating layer 6. Then, a blanket tungsten layer 13 is deposited on the adhesion layer 12. The whole surface of the blanket tungsten layer 13 is etched back until a small hollow gap is formed at the upper end portion of the contact hole 11, to leave the blanket tungsten layer 13 only in the inside of the contact hole 11. Thereafter, an Al alloy layer is reflow-sputtered on the whole surface of the insulating layer 6 and the inside of the contact holes at a comparatively low temperature to form an upper level wiring layer 15. The surface unevenness produced in etch-back process can be planarized. A wiring having a good coverage, a good quality of layer, and a flat surface can be formed.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: July 7, 1998
    Assignee: Yamaha Corporation
    Inventors: Satoshi Hibino, Tetsuya Kuwajima
  • Patent number: 5716869
    Abstract: A method of manufacturing a semiconductor device having the steps of: forming an insulating layer on a substrate having a semiconductor surface; forming a contact hole in and through the insulating layer; forming a conductive film on the inner surface of the contact hole and on the surface of the insulating film; forming a vapor deposited titanium film on the inner wall of a vacuum chamber; placing the substrate formed with the conductive film in the vacuum chamber; and heating the substrate and reflowing the conductive film. A good wiring layer can be formed by suppressing generation of a void during a reflow process.
    Type: Grant
    Filed: September 10, 1996
    Date of Patent: February 10, 1998
    Assignee: Yamaha Corporation
    Inventors: Satoshi Hibino, Takahisa Yamaha
  • Patent number: 5705426
    Abstract: A method of forming conductive wiring on a semiconductor substrate. A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and tapered tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and tapered tungsten regions between the first and second barrier metal layers, preventing punch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: January 6, 1998
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino
  • Patent number: 5705429
    Abstract: After forming a contact hole in an insulator layer, which is formed on a substrate covering an impurity doped region, a Ti film, a TiN film (or TiON film), and an Al alloy (for example, an alloy of Al--Si--Cu) layer are sputtered (consecutively from the bottom level) for forming a wiring material layer. A wiring layer is formed by patterning the wiring material layer in accordance with a wiring pattern. Portions with a 0% coverage of the Al alloy layer are eliminated by sputtering the Al alloy layer with a substrate temperature in a range between 100.degree.and 150.degree. C.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: January 6, 1998
    Assignee: Yamaha Corporation
    Inventors: Takahisa Yamaha, Satoshi Hibino, Masaru Naito
  • Patent number: 5693629
    Abstract: A progesterone compound represented by the following formula (1): ##STR1## ?wherein R.sup.1 represents a C1-C23 hydrocarbon group!, and a neovascularization inhibitor containing the same as the active ingredient.The compound (1) has a potent neovascularization inhibitory effect and is hence useful in the treatment of malignant tumors, diabetic retinitis, rheumatism, etc.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: December 2, 1997
    Assignee: Meiji Milk Products Co., Ltd.
    Inventors: Satoshi Hibino, Eiichi Sugino, Tetsuya Kohno, Shiho Fujimori, Hideo Nemoto, Yoshitatsu Ichihara, Yoshio Sato
  • Patent number: 5637924
    Abstract: A plurality of contact holes having different sizes are formed in an insulating film formed on the substrate. A first barrier metal layer is formed on the insulating film, and a tungsten layer is uniformly formed on the first barrier metal layer. The tungsten layer is etched back to form plug-shaped tungsten regions in small contact holes and sloped tungsten regions in large contact holes. The central area of the first barrier metal layer in the large contact hole is exposed. A second barrier metal layer is formed covering the plug-shaped tungsten region and the tapered tungsten region and the exposed first barrier metal layer and sandwiching the plug-shaped and sloped tungsten regions between the first and second barrier metal layers, preventing pinch-through of Al atoms from an Al layer to be thereafter formed, into the substrate, even when the first barrier metal layer is damaged during etch-back.
    Type: Grant
    Filed: June 23, 1995
    Date of Patent: June 10, 1997
    Assignee: Yamaha Corporation
    Inventor: Satoshi Hibino