Patents by Inventor Satoshi HIGANO

Satoshi HIGANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150006343
    Abstract: Devices, methods, and programs for billing for electric power. A billing method may include generating billing information for an amount related to electric power transmitted by a power supply device, performing a billing process based on the billing information, and selectively transmitting electric power based on the result of the billing process. A power supply device may include a billing information generating unit, a billing processing unit, and a power control unit. Another billing method may include determining whether billing information has been received, performing a billing process after it is determined that the billing information has been received, transmitting a response signal to a power supply device, and providing notice regarding information related to the billing process. A power receiving device may include a billing processing unit, a power control unit, and a notice control unit.
    Type: Application
    Filed: January 31, 2013
    Publication date: January 1, 2015
    Applicant: Sony Corporation
    Inventors: Yoichiro Sako, Taro Tadano, Takanori Washiro, Kazuyoshi Takemura, Kuniya Hayashi, Isao Soma, Kayoko Tanaka, Satoshi Higano, Kazutoshi Serita
  • Publication number: 20140375138
    Abstract: Devices, methods, and programs for providing a notice indicating whether a device supports an authentication function. A method for providing notice may include performing communication with a device, making a determination whether the device is a power supply target, selectively transmitting power to the device based on a result of the determination, and providing a notice indicating whether the device supports an authentication function based on the result of the determination. A power supply device may include a communication unit, a determining unit, a power control unit, and a notice control unit. Another method for providing notice may include performing communication with a device, and providing a notice indicating whether the power supply device supports the authentication function based on a result of the communication. A power receiving device may include a communication unit and a notifying unit.
    Type: Application
    Filed: January 28, 2013
    Publication date: December 25, 2014
    Applicant: Sony Corporation
    Inventors: Yoichiro Sako, Takanori Washiro, Kazuyoshi Takemura, Kuniya Hayashi, Isao Soma, Kayoko Tanaka, Satoshi Higano, Kazutoshi Serita
  • Publication number: 20140332808
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×1018 atoms/cm3, preferably lower than or equal to 1×1018 atoms/cm3.
    Type: Application
    Filed: July 29, 2014
    Publication date: November 13, 2014
    Inventors: Katsuaki TOCHIBAYASHI, Satoshi HIGANO, Shunpei YAMAZAKI
  • Publication number: 20140327000
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield to achieve high productivity. In the manufacture of a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are sequentially stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film, the source electrode layer and the drain electrode layer are formed through an etching step and then a step for removing impurities which are generated by the etching step and exist on a surface of the oxide semiconductor film and in the vicinity thereof is performed.
    Type: Application
    Filed: July 21, 2014
    Publication date: November 6, 2014
    Inventors: Katsuaki TOCHIBAYASHI, Satoshi HIGANO, Shunpei YAMAZAKI
  • Patent number: 8846459
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield to achieve high productivity. In the manufacture of a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are sequentially stacked and a source electrode layer and a drain electrode layer are provided in contact with the oxide semiconductor film, the source electrode layer and the drain electrode layer are formed through an etching step and then a step for removing impurities which are generated by the etching step and exist on a surface of the oxide semiconductor film and in the vicinity thereof is performed.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Satoshi Higano, Shunpei Yamazaki
  • Patent number: 8815640
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×1018 atoms/cm3, preferably lower than or equal to 1×1018 atoms/cm3.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: August 26, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Satoshi Higano, Shunpei Yamazaki
  • Publication number: 20130138256
    Abstract: There is provided a power control apparatus including an input unit to which attribute information regarding a type of generation of power is input, a determination unit configured to determine the type of generation of the power corresponding to the attribute information according to the attribute information, and a power control unit configured to control use of the power according to a determination result by the determination unit.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 30, 2013
    Inventors: Yoichiro SAKO, Yasuhiro YAMADA, Akira TANGE, Satoshi HIGANO