Patents by Inventor Satoshi Inada
Satoshi Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190214362Abstract: A laser bonding apparatus, a method of bonding a plurality of semiconductor devices arranged on a main substrate of a workpiece, to the main substrate, and a method of manufacturing a semiconductor package, the laser bonding apparatus including a chamber having a transmissive window and in which a workpiece is accommodatable; a gas supply conduit connected to the chamber and configured to supply a gas at an elevated pressure relative to a pressure outside of the chamber; and a laser generator arranged outside the chamber and configured to irradiate the workpiece accommodated in the chamber, through the transmissive window.Type: ApplicationFiled: January 10, 2019Publication date: July 11, 2019Inventors: Jun-su LIM, Satoshi INADA
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Publication number: 20180337083Abstract: A method of processing a substrate includes attaching a first surface of a planarization film to a processing target substrate, disposing an electrostatic carrier onto a second surface opposite the first surface of the planarization film, fixing the processing target substrate to the electrostatic carrier by supplying power to the electrostatic carrier, and performing processing on the processing target substrate.Type: ApplicationFiled: January 15, 2018Publication date: November 22, 2018Inventors: Satoshi Inada, Je-kook Lyu, Yoshihisa Saimoto, Yoon-seok Song, Kyung-hak Lee, Ki-hyun Jung
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Patent number: 9664972Abstract: A lateral electric field type liquid crystal display apparatus includes a first substrate on which pixels are disposed in a matrix shape, each of the pixels including a plurality of signal wirings and a plurality of scanning wirings which intersect each other, a switching element provided in a region adjacent to a portion in which the signal wiring and the scanning wiring intersect or on the scanning wiring, a pixel electrode connected to the switching element, and a counter electrode to which a common potential is supplied from a common potential wiring; a second substrate provided to face the first substrate; and a liquid crystal provided between the first and second substrates, wherein a first electric field shield electrode, which is set to the common potential, is provided between the signal wiring and the first substrate, and the first electric field shield electrode is electrically connected with a first wiring which supplies the common potential to the first electric field shield electrode, within a dType: GrantFiled: July 23, 2015Date of Patent: May 30, 2017Assignee: NLT TECHNOLOGIES, LTD.Inventors: Takeshi Sasaki, Satoshi Inada
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Patent number: 9437505Abstract: Carry out a vapor etching step of cleaning an inside of a chamber of a vapor phase growth apparatus by vapor etching using HCl gas (S1). Carry out an annealing step of sequentially annealing a predetermined number of silicon wafers, one by one, in a non-oxidizing atmosphere (S2, S3). Repeat the vapor etching step and the annealing step a prescribed number of times. After having carried out the vapor etching step and the annealing step the prescribed number of times (S4: Yes), collect contaminants on the surface of each of the wafers, and measure the Mo concentration using ICP-MS (S5). Evaluate the cleanliness of the vapor phase growth apparatus on the basis of each Mo concentration value and the relationship between the Mo concentrations (S6). Thus, provided is a method with which it is possible to measure, with high sensitivity, the contamination amount of a vapor phase growth apparatus.Type: GrantFiled: September 26, 2013Date of Patent: September 6, 2016Assignee: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Takeshi Arai, Satoshi Inada
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Publication number: 20160026051Abstract: A lateral electric field type liquid crystal display apparatus includes a first substrate on which pixels are disposed in a matrix shape, each of the pixels including a plurality of signal wirings and a plurality of scanning wirings which intersect each other, a switching element provided in a region adjacent to a portion in which the signal wiring and the scanning wiring intersect or on the scanning wiring, a pixel electrode connected to the switching element, and a counter electrode to which a common potential is supplied from a common potential wiring; a second substrate provided to face the first substrate; and a liquid crystal provided between the first and second substrates, wherein a first electric field shield electrode, which is set to the common potential, is provided between the signal wiring and the first substrate, and the first electric field shield electrode is electrically connected with a first wiring which supplies the common potential to the first electric field shield electrode, within a dType: ApplicationFiled: July 23, 2015Publication date: January 28, 2016Applicant: NLT TECHNOLOGIES, LTD.Inventors: Takeshi SASAKI, Satoshi INADA
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Publication number: 20150243566Abstract: Carry out a vapor etching step of cleaning an inside of a chamber of a vapor phase growth apparatus by vapor etching using HCl gas (S1). Carry out an annealing step of sequentially annealing a predetermined number of silicon wafers, one by one, in a non-oxidizing atmosphere (S2, S3). Repeat the vapor etching step and the annealing step a prescribed number of times. After having carried out the vapor etching step and the annealing step the prescribed number of times (S4: Yes), collect contaminants on the surface of each of the wafers, and measure the Mo concentration using ICP-MS (S5). Evaluate the cleanliness of the vapor phase growth apparatus on the basis of each Mo concentration value and the relationship between the Mo concentrations (S6). Thus, provided is a method with which it is possible to measure, with high sensitivity, the contamination amount of a vapor phase growth apparatus.Type: ApplicationFiled: September 26, 2013Publication date: August 27, 2015Inventors: Takeshi Arai, Satoshi Inada
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Patent number: 9111965Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor regions each having a protruded shape provided on a substrate, the first semiconductor region including a first source, a first drain, and a first channel provided between the first source and the first drain and extending in a first direction from the first source to the first drain, the first channel having a first width in a second direction perpendicular to the first direction, and the second semiconductor region including a second source, a second drain, and a second channel provided between the second source and the second drain and extending in a third direction from the second source to the second drain, the second channel having a second width in a fourth direction perpendicular to the third direction that is wider than the first width of the first channel.Type: GrantFiled: November 19, 2013Date of Patent: August 18, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kensuke Ota, Masumi Saitoh, Toshinori Numata, Chika Tanaka, Satoshi Inada
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Publication number: 20150072440Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the non-magnetic layer, and patterning the second magnetic layer by a RIE using an etching gas including a noble gas and a hydrocarbon gas.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Inventors: Satoshi INADA, Kazuhiro TOMIOKA, Satoshi SETO, Masatoshi YOSHIKAWA
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Publication number: 20150072439Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Inventors: Kazuhiro TOMIOKA, Satoshi SETO, Masatoshi YOSHIKAWA, Satoshi INADA
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Patent number: 8956882Abstract: According to one embodiment, a method of manufacturing a magnetoresistive element, the method includes forming a first non-magnetic layer on a first magnetic layer, forming a second magnetic layer on the first non-magnetic layer, forming a second non-magnetic layer on the second magnetic layer, forming a third magnetic layer on the second non-magnetic layer, patterning the third magnetic layer by a RIE using an etching gas including a noble gas and a nitrogen gas until a surface of the second non-magnetic layer is exposed, and patterning the second non-magnetic layer and the second magnetic layer after patterning of the third magnetic layer.Type: GrantFiled: March 7, 2014Date of Patent: February 17, 2015Inventors: Kazuhiro Tomioka, Satoshi Seto, Masatoshi Yoshikawa, Satoshi Inada
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Patent number: 8796594Abstract: A semiconductor manufacturing equipment is provided herein. The semiconductor manufacturing equipment includes a heater element configured to heat a wafer, a first connection part and a second connection part integrated with the heater element, a first electrode electrically contacted with and fixed to the first connection part on a first surface of the first electrode, and a second electrode electrically contacted with and fixed to the second connection part on a second surface of the second electrode. The second surface is perpendicular to the direction of the first surface, and the heater element produces heat by applying a voltage between the first electrode and the second electrode.Type: GrantFiled: March 16, 2007Date of Patent: August 5, 2014Assignee: NuFlare Technology, Inc.Inventors: Hideki Arai, Satoshi Inada, Yoshikazu Moriyama, Noriki Juumatsu
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Publication number: 20140138690Abstract: A semiconductor device according to an embodiment includes: first and second semiconductor regions each having a protruded shape provided on a substrate, the first semiconductor region including a first source, a first drain, and a first channel provided between the first source and the first drain and extending in a first direction from the first source to the first drain, the first channel having a first width in a second direction perpendicular to the first direction, and the second semiconductor region including a second source, a second drain, and a second channel provided between the second source and the second drain and extending in a third direction from the second source to the second drain, the second channel having a second width in a fourth direction perpendicular to the third direction that is wider than the first width of the first channel.Type: ApplicationFiled: November 19, 2013Publication date: May 22, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kensuke OTA, Masumi Saitoh, Toshinori Numata, Chika Tanaka, Satoshi Inada
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Patent number: 8524609Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.Type: GrantFiled: September 12, 2011Date of Patent: September 3, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Inada, Mitsuhiro Omura, Hisataka Hayashi
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Publication number: 20120214308Abstract: An aspect of the present embodiment, there is provided a method of fabricating a semiconductor device including providing a film to be processed above a semiconductor substrate, providing a negative-type resist and a photo-curable resist in order, pressing a main surface of a template onto the photo-curable resist, the main surface of the template having a concavo-convex pattern with a light shield portion provided on at least a part of a convex portion, irradiating the template with light from a back surface of the template, developing the negative-type resist and the photo-curable resist so as to print the concavo-convex pattern of the template on the negative-type resist and the photo-curable resist, and etching the film to be processed by using the concavo-convex pattern printed on the negative-type resist and the photo-curable resist as a mask.Type: ApplicationFiled: September 12, 2011Publication date: August 23, 2012Inventors: Satoshi INADA, Mitsuhiro OMURA, Hisataka HAYASHI
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Patent number: 8199309Abstract: Disclosed is a liquid crystal display device that includes a TFT substrate. A plurality of gate lines and a plurality of common lines extend in a first direction on the TFT substrate. Drain lines extend in a second direction substantially perpendicularly to these lines. Bus lines are located outside a display area and are extending parallel to the drain lines. Common line terminals are provided on either side of each block that is constituted by a predetermined number of gate terminals. The common line terminals and the lead lines therefore are formed on the same layer as the drain lines and are connected to the bus lines on the same layer without any contacts being used. Resistance along the routes taken by common lines can be reduced.Type: GrantFiled: August 18, 2009Date of Patent: June 12, 2012Assignee: NEC CorporationInventors: Takayuki Konno, Satoshi Inada, Yoshiro Kitagawa, Shinichi Nishida
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Patent number: 8007588Abstract: A vapor phase epitaxial growth method using a vapor phase epitaxy apparatus having a chamber, a support structure holding thereon a substrate in the chamber, a first flow path supplying a reactant gas for film formation on the substrate and a second flow path for exhaust of the gas, said method includes rotating the substrate, supplying the reactant gas and a carrier gas to thereby perform vapor-phase epitaxial growth of a semiconductor film on the substrate, and during the vapor-phase epitaxial growth of the semiconductor film on the substrate, controlling process parameters to make said semiconductor film uniform in thickness, said process parameters including flow rates and concentrations of the reactant gas and the carrier gas, a degree of vacuum within said chamber, a temperature of the substrate, and a rotation speed of said substrate.Type: GrantFiled: March 20, 2007Date of Patent: August 30, 2011Assignee: NuFlare Technology, Inc.Inventors: Hideki Ito, Satoshi Inada, Yoshikazu Moriyama
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Publication number: 20090310078Abstract: Disclosed is a liquid crystal display device that includes a TFT substrate. A plurality of gate lines and a plurality of common lines extend in a first direction on the TFT substrate. Drain lines extend in a second direction substantially perpendicularly to these lines. Bus lines are located outside a display area and are extending parallel to the drain lines. Common line terminals are provided on either side of each block that is constituted by a predetermined number of gate terminals. The common line terminals and the lead lines therefor are formed on the same layer as the drain lines and are connected to the bus lines on the same layer without any contacts being used. Resistance along the routes taken by common lines can be reduced.Type: ApplicationFiled: August 18, 2009Publication date: December 17, 2009Applicant: NEC LCD TECHNOLOGIES, LTD.Inventors: Takayuki KONNO, Satoshi INADA, Yoshiro KITAGAWA, Shinichi NISHIDA
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Patent number: 7609354Abstract: Disclosed is a liquid crystal display device that includes a TFT substrate. A plurality of gate lines and a plurality of common lines extend in a first direction on the TFT substrate. Drain lines extend in a second direction substantially perpendicularly to these lines. Bus lines are located outside a display area and are extending parallel to the drain lines. Common line terminals are provided on either side of each block that is constituted by a predetermined number of gate terminals. The common line terminals and the lead lines therefor are formed on the same layer as the drain lines and are connected to the bus lines on the same layer without any contacts being used. Resistance along the routes taken by common lines can be reduced.Type: GrantFiled: March 28, 2005Date of Patent: October 27, 2009Assignee: NEC LCD Technologies, LtdInventors: Takayuki Konno, Satoshi Inada, Yoshiro Kitagawa, Shinichi Nishida
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Patent number: 7570339Abstract: A liquid crystal display device includes an active matrix substrate and a counter substrate opposing each other with a gap therebetween defined by a plurality of columnar spacers. The active matrix substrate has a plurality of spacer holes each receiving therein a corresponding one of the columnar spacers, and a plurality of dummy spacer holes aligned with the spacer holes and each receiving therein no columnar spacer.Type: GrantFiled: April 20, 2005Date of Patent: August 4, 2009Assignee: NEC LCD Technologies, Ltd.Inventors: Tsutomu Kadotani, Satoshi Inada, Takashi Kamino, Yusuke Nogami
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Publication number: 20070221657Abstract: Semiconductor manufacturing equipment includes a heater element configured to heat a wafer, a first connection part and a second connection part which are integrated with the heater element, configured to apply voltages to the heater element, a first electrode contacted with and fixed to the first connection part on a first surface of the first electrode configured to be to apply a voltage to the first connection part, a second electrode which is contacted with and fixed to the second connection part on a second surface of the second electrode, configured to apply a voltage to the second connection part, and the second surface is perpendicular to the direction of the first surface.Type: ApplicationFiled: March 16, 2007Publication date: September 27, 2007Inventors: Hideki Arai, Satoshi Inada, Yoshikazu Moriyama, Noriki Juumatsu