Abstract: The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Abstract: To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.

Abstract: Introduced in an image data encoding device is a logic-memory combined chip in which a memory device and a signal processing device are combined. A logic part and a memory part can be connected to each other with a wide bus, allowing to improve processing capability of data transfer. However, the memory part of the logic-memory combined chip has a small capacity, so that an attempt to increase the capacity will lead to upsizing of the chip, resulting in an increase in costs. Therefore, in a processing that data transfer results in bottlenecks (i.e., motion search), image data is transferred to/from an internal memory capable of transferring data at high speed. In a processing that high-speed data transfer is not required, image data is transferred to/from an external memory.

Abstract: The number of stuff bytes to be inserted is calculated using a stuff code inserter in a difference detection circuit, inserted as a stuff code into a bit stream of coded data and stored into a bit stream buffer. The stuff code is detected in a multiplexed bit stream read out from the bit stream buffer, read of a coded bit stream is ceased and stuff bytes indicated by the stuff code are inserted into the coded bit stream. Therefore, stuff bytes generated in great amount can be easily inserted into an output bit stream even with a small data transfer capacity of the bit stream buffer.

Abstract: A coding parameter obtained by a first coding processing is transferred from signal processing sections (403) to (406) to a parameter input/output section (408) through a coding control section (407), and the parameter input/output section (408) stores the coding parameter in an external DRAM (411) through an SDRAM interface section (410). In a second coding processing, the coding parameter stored in the external DRAM (411) is transferred to the parameter input/output section (408) through the external DRAM (411), and the parameter input/output section (408) gives the acquired coding parameter to the signal processing sections (403) to (406) through the coding control section (407).

Abstract: The data multiplexing device includes a header information memory storing header information, ES buffers holding encoded data of a plurality of media, an output buffer holding packetized data, and a transfer controlling unit controlling a transfer of the header information stored in the header information memory and the encoded data held in the ES buffers and writing into the output buffer as the packetized data. The transfer controlling unit can generate the packetized data simply by controlling the transfer of the header information stored in the header information memory and the encoded data held in the ES buffers, whereby the media multiplexing can be readily achieved.

Abstract: A plurality of motion detecting units of which at least a template block size, i.e., the number of estimation pixels, or a search area size is different among the motion detecting units are used adaptively according to the characteristic of, or the prediction coding type of, a target picture. This enables efficient motion vector detection to be accomplished without increasing the amount of hardware or power consumption.

Abstract: An encoding device includes a processor unit controlling an overall operation and at the same time having a software for executing an audio encoding process, a video encoding unit to execute a video encoding process, a multiplex process unit to execute a system process and a timing control unit to generate a timing signal for activating an audio encoding process, a video encoding process and a system process, all of these elements are mountable on the same substrate. Each of a control process for controlling the audio encoding process, the video encoding process and system process is executed as an interrupt process. The processor unit includes an interrupt control circuit. The interrupt control circuit selects, based on a predetermined priority, one interrupt process corresponding to at least one generated timing signal.

Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: An image data coding apparatus includes: a memory interface which controls reading/writing of data from/to an external memory; an MPEG2 processing unit for performing a compression-coding process using a first compression ratio; and a coder/decoder which is provided between the MPEG2 processing unit and the memory interface, which performs a compression-coding process using a second compression ratio lower than the first compression ratio on data outputted from an image data coding unit to the external memory, and which performs a decoding process on data outputted from the external memory to the image data coding unit.

Abstract: A frequency of an operating clock signal to be supplied to a video interface section, an audio interface section, a motion predicting section for conducting motion prediction of image data, a loop processing section for predictive-coding each image data based on a plurality of image data at different points of time on a time base and the motion prediction result, a DSP (Digital Signal Processor) section for coding an audio signal, and a DRAM (Dynamic Random Access Memory) interface section is separately adjusted according to the processing load of an image coding integrated circuit.

Abstract: A search MB determination unit determines whether or not an object macro block is a macro block on which a motion search is carried out. A motion vector determination unit selects an optimal vector of a macro block determined not to carry out a motion search by the search MB determination unit from among neighboring macro blocks. Accordingly, it becomes possible, in comparison with a motion search apparatus that carries out a motion search on every macro block, to eliminate the amount of data to be operated required for the motion search while preventing image quality deterioration.

Abstract: The control circuit controls output of template block data held in the input section such that a plurality of operation units within the operation section are provided with data of unadjacent template blocks that are different from each other. The operation units within the operation section detect motion vectors according to the template block data provided thereto. Thus, motion vector detection in the template blocks except for those in a region on a display screen requiring no motion vector detection is distributed in the plurality of operation units. Accordingly, the motion vector search can be performed in a wider range in a vertical or horizontal direction than in the conventional case within the same operation time.

Abstract: Element processors (PE00 to PE33) included in a processor array (7) store pixel values of a search window, shifting them forward. Further, only hatched element processors (PE00, PE02, PE11, PE13, PE20, PE22, PE31, PE33) store pixel values of a template block, and compare them with the pixel values in the search to evaluate a similarity of pixel values. In other words, the pixel values of the template block are skipped and the pixel values which are left after skipping are compared. Therefore, it is possible to cut a hardware volume.

Abstract: When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Abstract: Introduced in an image data encoding device is a logic-memory combined chip in which a memory device and a signal processing device are combined. A logic part and a memory part can be connected to each other with a wide bus, allowing to improve processing capability of data transfer. However, the memory part of the logic-memory combined chip has a small capacity, so that an attempt to increase the capacity will lead to upsizing of the chip, resulting in an increase in costs. Therefore, in a processing that data transfer results in bottlenecks (i.e., motion search), image data is transferred to/from an internal memory capable of transferring data at high speed. In a processing that high-speed data transfer is not required, image data is transferred to/from an external memory.

Abstract: To provide an image compression coding apparatus and method capable of minimizing a deterioration in picture quality which is caused on a reproduced image during an overflow of an output buffer. A picture top detector (7A) executes a picture top detection processing for discarding image compression data (S2) until a top of a picture of the image compression data (S2) is detected during detection of a start address, and restarts a normal operation after detecting the top of the picture. A processor (5) brings a detection start register (8) into a set state and causes the picture top detector (7A) to execute the picture top detection processing during an overflow of an output buffer (3a), and executes an interruption processing of rewriting, as a value of a write address register (9), an address where a top of an overflow picture to be a picture causing the overflow is stored.

Abstract: A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode.

Abstract: An encoding device includes a processor unit controlling an overall operation and at the same time having a software for executing an audio encoding process, a video encoding unit to execute a video encoding process, a multiplex process unit to execute a system process and a timing control unit to generate a timing signal for activating an audio encoding process, a video encoding process and a system process, all of these elements are mountable on the same substrate. Each of a control process for controlling the audio encoding process, the video encoding process and system process is executed as an interrupt process. The processor unit includes an interrupt control circuit. The interrupt control circuit selects, based on a predetermined priority, one interrupt process corresponding to at least one generated timing signal.