Abstract: The number of stuff bytes to be inserted is calculated using a stuff code inserter in a difference detection circuit, inserted as a stuff code into a bit stream of coded data and stored into a bit stream buffer. The stuff code is detected in a multiplexed bit stream read out from the bit stream buffer, read of a coded bit stream is ceased and stuff bytes indicated by the stuff code are inserted into the coded bit stream. Therefore, stuff bytes generated in great amount can be easily inserted into an output bit stream even with a small data transfer capacity of the bit stream buffer.

Abstract: Disclosed is an image coding method and apparatus for preventing a coding quantity of coding data from being increased when a redundancy between image planes is low. A selector outputs either an optimum motion vector output from a motion vector detecting device or a motion vector output from a motion vector storing section to a real time image coding device for performing coding on the basis of an evaluation value output from the motion vector detecting device. If it is decided, according to the evaluation value, that a redundancy between a reference image plane and a coding object image plane is low, the motion vector is selected so that the coding quantity of the coding data can be prevented from being increased.

Abstract: Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.

Abstract: An evaluation value operation part computes evaluation values of a template block and a search window block in accordance with respective ones of a plurality of predictive modes in parallel with each other, and a candidate vector determination part decides candidate vectors indicating optimum vectors in accordance with the computed evaluation values and on the basis of priority levels from a priority generation part. In accordance with these candidate vectors, an optimum vector decision part decides the optimum vectors for the respective predictive modes. Thus provided is an image coding system which can reduce the amount of codes of motion vectors with excellent picture quality.

Abstract: Each of element processors arranged in correspondence to pixels of a template block and a search window block respectively includes an A register and a B register provided in parallel with each other for storing search window block pixel data respectively, and a T register for storing template block pixel data. Motion vector evaluation value calculation is performed through a first one of the A and B registers and the pixel data stored in the T register, while operated data is transferred to the second one of the A and B registers from the first one of the A and B registers in parallel with the calculation operation, for storing head search window block pixel data of a next search window. A motion vector is detected at a high speed in excellent coding efficiency.

Abstract: A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.

Abstract: It is an object of the present invention to realize bypass of input data in a macro-cell such as a FIFO memory etc. to facilitate test and evaluation about other macro-cells. A bypass route (6) is provided between an input port (DI) and an output port (DO) in a FIFO memory (1) and a data bypassing selector (8) is further provided for selecting the bypass route (6) and a sense amplifier (7) of a read bit line (R.BL). Then, in the test mode, a first selector control signal (S) is set to an L level and a second selector control signal (S) of opposite phase is set to an H level. Thus, in the test mode, a data inputted from the input port (DI) is outputted from the output port (DO) by way of the bypass route (6) without via memory cells (MC1-MCX).

Abstract: Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.

Abstract: In order to generate zigzag addresses for Discrete Cosine Transformation DCT data arranged in the form of a square matrix, row differentials (.DELTA.y) and column differentials (.DELTA.x) being differentials of row addresses (y) and column addresses (x) are previously stored to be successively read out (steps S12 and S13). The row differentials (.DELTA.y) and the column differentials (.DELTA.x) are added to the row addresses (y) and the column addresses (x) respectively, to newly obtain zigzag addresses (steps S14 and S15). Thus, the amount data to be stored can be reduced. Further, it is possible to further reduce the amount of data to be stored by compressing data through regularity of the row differentials (.DELTA.y) and the column differentials (.DELTA.x).

Abstract: A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value.

Abstract: An information processing system including processors, and an interrupt controller responsive to an interrupt request signal from the processors for executing an interrupt process control of processes carried out by the processors. The interrupt controller includes an interrupt process execution device that does not have a multiple interrupt processing function, and an interrupt acceptance device. The interrupt acceptance device has an interrupt reservation signal input terminal, and responds to an interrupt request signal for making determination whether an interrupt is permitted. If interrupt is permitted, an interrupt request generation signal is applied to a corresponding interrupt request generation signal input terminal of the interrupt process execution device. Each of the processors includes an interrupt request signal output circuit and a processing circuit.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

Abstract: An output buffer circuit comprises a P channel MOS transistor connected between a power supply terminal and an output terminal, an N channel MOS transistor connected between a ground terminal and an output terminal, a capacitance connected to a ground terminal, and a switch formed of an N channel MOS transistor connected between the output terminal and the capacitance. In charging a load, first, charge stored in the capacitance is supplied to the output terminal, and subsequently the P channel MOS transistor is turned on. In discharging the load, first, charge is supplied from the output terminal to the capacitance, and subsequently the N channel MOS transistor is turned on.