Patents by Inventor Satoshi Matsuda

Satoshi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080286931
    Abstract: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region.
    Type: Application
    Filed: August 14, 2007
    Publication date: November 20, 2008
    Inventor: Satoshi MATSUDA
  • Publication number: 20080057642
    Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.
    Type: Application
    Filed: October 25, 2007
    Publication date: March 6, 2008
    Inventor: Satoshi Matsuda
  • Patent number: 7332380
    Abstract: According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy pattern region and a dummy pattern prohibition region, dividing the dummy pattern region into dummy pattern unit regions, setting a plurality of inspection areas in the dummy pattern region and the dummy pattern prohibition region, the inspection area closing round at least the two or more dummy pattern unit regions, a part of the one dummy pattern unit region overlapping a part of another dummy pattern unit region, calculating a tentative pattern-covering fraction of a dummy pattern, the dummy pattern being formed of the dummy pattern unit region in the inspection area, calculating a final pattern-covering fraction of the dummy pattern unit region, the final pattern-covering fraction being obtained by averaging the tentative pattern-covering fract
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: February 19, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Matsuda
  • Publication number: 20070259507
    Abstract: In a manufacturing method of semiconductor device, initially, a trench pattern is laid out along a <100> direction of a (100) silicon substrate. Next, a trench is formed in the silicon substrate based on the laid-out trench pattern. Further, the silicon substrate with the trench formed therein is annealed in a low-pressure reducing atmosphere to cause silicon migration. This reduces the radius of curvature of a corner portion of the formed trench pattern. Consequently, changes of the contact area with an electrode and a contact can be suppressed in an active area isolated by the trench pattern, and characteristic deterioration caused by changes of the contact area can be suppressed.
    Type: Application
    Filed: March 20, 2007
    Publication date: November 8, 2007
    Inventor: Satoshi Matsuda
  • Patent number: 7288470
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Atsushi Azuma
  • Patent number: 7268097
    Abstract: A desulfurizing agent comprising a silica-alumina carrier having an Si/Al mole ratio of 10 or less and nickel carried thereon; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a specific surface area of pores having a pore diameter of 3 nm or less of 100 m2/g or more; an Ni-Cu based desulfurizing agent comprising a carrier and, carried thereon, (A) nickel, (B) copper, and (C) an alkali metal or another metal; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a hydrogen adsorption capacity of 0.4 mmol/g or more; and methods for producing these nickel-based and nickel-copper-based desulfurizing agents. The above desulfurizing agents are capable of adsorbing and removing with good efficiency the sulfur contained in hydrocarbons derived from petroleum to a content of 0.2 wt. ppm or less and have a long service life.
    Type: Grant
    Filed: April 2, 2001
    Date of Patent: September 11, 2007
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Hisashi Katsuno, Satoshi Matsuda, Kazuhito Saito, Masahiro Yoshinaka
  • Patent number: 7265400
    Abstract: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: September 4, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Matsuda
  • Publication number: 20070184623
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.
    Type: Application
    Filed: March 28, 2007
    Publication date: August 9, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Matsuda, Atsushi Azuma
  • Patent number: 7214595
    Abstract: A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Kawasaki, Satoshi Matsuda, Hisakazu Matsumori, Hidenori Shibata, Kumi Okuwada
  • Publication number: 20070069267
    Abstract: A semiconductor device comprises static random access memory (SRAM) cells formed in a semiconductor substrate, first deep trenches isolating each boundary of an n-well and a p-well of the SRAM cells, second deep trenches isolating the SRAM cells into each unit bit cell, and at least one or more contacts taking substance voltage potentials in regions isolated by the first and second deep trenches. Then, the device becomes possible to improve a soft error resistance without increasing the device in size.
    Type: Application
    Filed: September 12, 2006
    Publication date: March 29, 2007
    Inventor: Satoshi Matsuda
  • Patent number: 7183168
    Abstract: A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a suicide film which extends from the N type diffusion layer over to the boundary region and the P-type diffusion layer. A boundary region between the P-type and N-type diffusion layers is formed in the selected portion.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: February 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Kazuya Ohuchi
  • Publication number: 20060288827
    Abstract: Torque necessary for cutting band-like paper is properly distributed to both of the preceding motor and the following motor, thereby making it possible to accurately cut the band-like paper.
    Type: Application
    Filed: April 28, 2005
    Publication date: December 28, 2006
    Applicant: Mitsubishi Heavy Industrial, Ltd.
    Inventors: Hiroshi Ishibuchi, Satoshi Matsuda, Kuniaki Wakusawa, Katsuaki Takasaki
  • Patent number: 7145215
    Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: December 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
  • Publication number: 20060157789
    Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.
    Type: Application
    Filed: December 22, 2005
    Publication date: July 20, 2006
    Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
  • Publication number: 20060094190
    Abstract: According to an aspect of the present invention, there is provided a pattern design method of a semiconductor device, including preparing design pattern data, separating a pattern region of a semiconductor device on the basis of the design pattern data into a dummy pattern region and a dummy pattern prohibition region, dividing the dummy pattern region into dummy pattern unit regions, setting a plurality of inspection areas in the dummy pattern region and the dummy pattern prohibition region, the inspection area closing round at least the two or more dummy pattern unit regions, a part of the one dummy pattern unit region overlapping a part of another dummy pattern unit region, calculating a tentative pattern-covering fraction of a dummy pattern, the dummy pattern being formed of the dummy pattern unit region in the inspection area, calculating a final pattern-covering fraction of the dummy pattern unit region, the final pattern-covering fraction being obtained by averaging the tentative pattern-covering fract
    Type: Application
    Filed: August 19, 2005
    Publication date: May 4, 2006
    Inventor: Satoshi Matsuda
  • Publication number: 20060076603
    Abstract: A semiconductor device is provided with a semiconductor substrate comprising element isolation regions and an element region surrounded by the element isolation regions, a first polysilicon layer formed in the element region of the semiconductor substrate, an element-isolating insulation film formed in the element isolation region of the semiconductor substrate, a second polysilicon layer formed on the element-isolating insulation film, a first silicide layer formed on the first polysilicon layer. And the device further comprising a second silicide layer formed on the second polysilicon layer and being thicker than the first silicide layer.
    Type: Application
    Filed: September 15, 2005
    Publication date: April 13, 2006
    Inventor: Satoshi Matsuda
  • Patent number: 7009273
    Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: March 7, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
  • Publication number: 20050106801
    Abstract: A method of manufacturing a semiconductor device includes implanting germanium ions into a selected portion of a semiconductor region containing at least silicon, forming P-type and N-type diffusion layers in the semiconductor region, and forming a silicide film which extends from the N type diffusion layer over to the boundary region and the P-type diffusion layer. A boundary region between the P-type and N-type diffusion layers is formed in the selected portion.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 19, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Matsuda, Kazuya Ohuchi
  • Publication number: 20050067665
    Abstract: An element isolation region for electrically isolating an element region where an element is to be formed is formed in a semiconductor substrate. A gate insulating film is formed on the semiconductor substrate in the element region. A gate electrode is formed on the gate insulating film. Source/drain regions are formed to be separated from each other in a surface region of the semiconductor substrate. The source/drain regions sandwich a channel region formed below the gate insulating film. Gate sidewall films are formed on the two side surfaces of the gate electrode. Silicide films are formed on the source/drain regions so as to be separated from the element isolation region.
    Type: Application
    Filed: August 13, 2004
    Publication date: March 31, 2005
    Inventor: Satoshi Matsuda
  • Patent number: 6841429
    Abstract: A semiconductor device is disclosed. The device includes a semiconductor region and P-type and N-type diffusion layers formed in the semiconductor region. The semiconductor region includes a germanium low-concentration region containing germanium of low concentration and a germanium high-concentration region containing germanium of high concentration. A boundary region between the P-type and N-type diffusion layers lies in the germanium high-concentration region. A silicide film is formed to extend from the P-type diffusion layer over to the boundary region and the N-type diffusion layer.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: January 11, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Kazuya Ohuchi