Patents by Inventor Satoshi Matsuda

Satoshi Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040266131
    Abstract: A method of producing semiconductor devices is provided, which makes it possible to bury a silicon oxide without shape deterioration in device isolation trenches. The method comprises the steps of: forming an etching resistive mask over a semiconductor substrate; etching the semiconductor substrate through an opening in the etching resistive mask to form a device isolation trench; forming a coat of a silazane perhydride polymer solution over the semiconductor substrate having the device isolation trench formed therein; vaporizing a solvent from the coat and then subjecting the coat to chemical reaction to form a film of silicon oxide; removing said film of the silicon oxide leaving a residue inside said device isolation trench; and heating said silicon oxide left in said device isolation trench for densification.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Inventors: Atsuko Kawasaki, Satoshi Matsuda, Hisakazu Matsumori, Hidenori Shibata, Kumi Okuwada
  • Publication number: 20040129998
    Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.
    Type: Application
    Filed: September 19, 2003
    Publication date: July 8, 2004
    Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
  • Publication number: 20040102012
    Abstract: A semiconductor device is disclosed. The device includes a semiconductor region and P-type and N-type diffusion layers formed in the semiconductor region. The semiconductor region includes a germanium low-concentration region containing germanium of low concentration and a germanium high-concentration region containing germanium of high concentration. A boundary region between the P-type and N-type diffusion layers lies in the germanium high-concentration region. A silicide film is formed to extend from the P-type diffusion layer over to the boundary region and the N-type diffusion layer.
    Type: Application
    Filed: November 19, 2003
    Publication date: May 27, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Kazuya Ohuchi
  • Publication number: 20040084731
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.
    Type: Application
    Filed: June 24, 2003
    Publication date: May 6, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Matsuda, Atsushi Azuma
  • Patent number: 6677660
    Abstract: A semiconductor device is disclosed. The device includes a semiconductor region and P-type and N-type diffusion layers formed in the semiconductor region. The semiconductor region includes a germanium low-concentration region containing germanium of low concentration and a germanium high-concentration region containing germanium of high concentration. A boundary region between the P-type and N-type diffusion layers lies in the germanium high-concentration region. A silicide film is formed to extend from the P-type diffusion layer over to the boundary region and the N-type diffusion layer.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: January 13, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Kazuya Ohuchi
  • Patent number: 6649462
    Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: November 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Azuma, Satoshi Matsuda
  • Patent number: 6642581
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: November 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Matsuda, Atsushi Azuma
  • Publication number: 20030113258
    Abstract: A desulfurizing agent comprising a silica-alumina carrier having an Si/Al mole ratio of 10 or less and nickel carried thereon; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a specific surface area of pores having a pore diameter of 3 nm or less of 100 m2/g or more; an Ni-Cu based desulfurizing agent comprising a carrier and, carried thereon, (A) nickel, (B) copper, and (C) an alkali metal or another metal; a desulfurizing agent for hydrocarbons derived from petroleum which comprises a carrier and a metal component carried thereon and has a hydrogen adsorption capacity of 0.4 mmol/g or more; and methods for producing these nickel-based and nickel-copper-based desulfurizing agents. The above desulfurizing agents are capable of adsorbing and removing with good efficiency the sulfur contained in hydrocarbons derived from petroleum to a content of 0.2 wt. ppm or less and have a long service life.
    Type: Application
    Filed: September 23, 2002
    Publication date: June 19, 2003
    Inventors: Hisashi Katsuno, Satoshi Matsuda, Kazuhito Saito, Masahiro Yoshinaka
  • Publication number: 20030073273
    Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.
    Type: Application
    Filed: November 13, 2002
    Publication date: April 17, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Azuma, Satoshi Matsuda
  • Patent number: 6515320
    Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: February 4, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Azuma, Satoshi Matsuda
  • Publication number: 20030022448
    Abstract: A gate insulating film is provided on a channel region. A gate electrode includes a lower part and an upper part. The lower part has a lower surface and sides, and the upper part has a lower surface. The lower surface of the lower part contacts the gate insulating film. The upper part is longer than the lower part in a lengthwise direction of a gate electrode. The first insulating film is interposed between the lower surface of the upper part of the gate electrode and a semiconductor substrate. The first insulating film surrounds at least the sides of the lower part of the gate electrode, which face drain and source regions, and having parts interposed between the lower surface of the upper part of the gate electrode and the semiconductor substrate and made thicker than the other parts.
    Type: Application
    Filed: November 8, 2001
    Publication date: January 30, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Azuma, Satoshi Matsuda
  • Publication number: 20020142529
    Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 3, 2002
    Inventors: Satoshi Matsuda, Atsushi Azuma
  • Patent number: 6333431
    Abstract: An object of the present invention is to provide a commercially advantageous process for preparing a fluoro benzoic acid. The process according to the present invention comprises either alkylating a fluoro benzoic acid of the formula wherein R1 is halogen, or reducing a fluoro benzoic acid of the formula wherein R1 is as defined above and R2 is lower alkyl to thereby produce a fluoro benzoic acid represented by the formula wherein R1 and R2 are as defined above.
    Type: Grant
    Filed: March 6, 2001
    Date of Patent: December 25, 2001
    Assignee: Otsuka Pharmaceutical Co., Ltd.
    Inventors: Akihiro Hashimoto, Satoshi Matsuda, Kuninori Tai, Hitoshi Tone, Takao Nishi, Jun-ichi Minamikawa, Michiaki Tominaga
  • Patent number: 6328880
    Abstract: Disclosed herein is a process for efficiently and stably producing high-quality kerosene and gas oil from crude oil or crude oil from which naphtha fraction is removed through the hydrotreatment of the crude oil by using a specific hydrotreatment catalyst; a process capable of prolonging the service life of the catalyst; a process capable of extending the continuous operation period of the process equipment; a process simplifying a petroleum refinery equipment; and the like. There are used, as hydrotreatment catalysts in the hydrotreatment of a hydrocarbon oil, the metals each belonging to any of the groups 6, 8, 9 and 10 of the Periodic Table which metals are supported on a carrier composed of alumina/boria, metal-containing aluminosilicate, alumina/an alkaline earth metal compound, alumina/phosphorus, alumina/titania or alumina/zirconia.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: December 11, 2001
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Mitsuru Yoshita, Nobuyuki Ohta, Ryuichiro Iwamoto, Takao Nozaki, Satoshi Matsuda, Toshihisa Konishi
  • Patent number: 5903027
    Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: May 11, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
  • Patent number: 5898203
    Abstract: A diffused server as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm-.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: April 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
  • Patent number: 5766965
    Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.
    Type: Grant
    Filed: December 5, 1994
    Date of Patent: June 16, 1998
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata
  • Patent number: 5698881
    Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Yoshitomi, Masanobu Saito, Hisayo Momose, Hiroshi Iwai, Yukihiro Ushiku, Mizuki Ono, Yasushi Akasaka, Hideaki Nii, Satoshi Matsuda, Yasuhiro Katsumata, Tatsuya Ooguro, Claudio Fiegna
  • Patent number: 5620908
    Abstract: A method of manufacturing a semiconductor device including selectively forming an element-isolating insulating layer on a surface of a semiconductor substrate to define active regions; forming a first insulating layer and removing respective portions thereof on surfaces of a second conductive type active region and a first active region of a first conductive type; oxidizing to form a gate oxide layer; forming and patterning a conductive layer to form a gate electrodes of MOS transistors and a base-extracting electrode of a bipolar transistor; forming an opening, in the base-extracting electrode, and a side wall insulating layer on an inner wall of the opening; removing first and second portions of the insulating layer to form an overhung portion; epitaxially growing a second conductive type semiconductor layer using the base-extracting electrode and active region of the first conductive type as a seed crystal; and selectively forming a first conductive type semiconductor layer that is to become an emitter tha
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: April 15, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumi Inoh, Yasuhiro Katsumata, Satoshi Matsuda, Chihiro Yoshino
  • Patent number: D412385
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: July 27, 1999
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Koji Murakami, Chikayo Eitoku, Chiaki Saito, Satoshi Matsuda