Abstract: A brake system includes an electric brake force generator which brakes a wheel using a driving force of an electric motor and an electric motor controller that performs a field-weakening control of the electric motor. The electric motor controller performs the field-weakening control of the electric motor which then operates the electric brake force generator. Thus, the rotational speed of the electric motor is increased when the field weakening control is performed by the electric motor controller thereby quickly activating the electric braking force generator to enhance response of brake force generation.

Abstract: With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction in a master thread being executed by a predetermined processor and when forkable, the slave thread is forked into other processor and when not forkable, the fork instruction is invalidated to execute an instruction subsequent to the fork instruction by the predetermined processor and then execute a group of instructions of the slave thread by the predetermined processor.

Abstract: A BBW type brake system which operates fluid pressure generators having electric motors as drive sources based on an electrical signal to brake a wheel, field weakening control of the electric motors is performed in the initial stage of operation of the fluid pressure generators to increase the rotational speed of the electric motors. Therefore, it is possible to reduce a time lag before the braking force actually generates after the electrical signal for operating the fluid pressure generators is outputted, thereby improving operational responsiveness. After the braking force actually generates, the field weakening control is cancelled to secure a required braking force with a sufficient torque.

Abstract: In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread generated form the above thread, the program cancels the child thread or makes invalid all the fork instructions other than the first fork instruction having succeeded in forking the child thread, hence to select one fork instruction for creating an effective child thread from a plurality of fork instructions existing within a parent thread, during the execution of the parent thread. Therefore, it can assure the Fork-Once limitation at a time of the program execution.

Abstract: Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address stored in this register. Each processor sends a thread stop notice to a thread controller when the value of its own program counter is coincident with the start address of the forked child thread and ends the execution of a parent thread when receiving a thread end permission from the thread controller.

Abstract: In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.

Abstract: A program parallelizing apparatus, a program parallelizing method and a program parallelizing program capable of creating a parallelized program of better parallel execution performance at a high speed. A fork point determination section extracts all fork points in a sequential processing program, and removes fork points with a static boost value satisfying a static rounding condition. A fork point combination determination section obtains a dynamic boost value and an exclusive fork set for each fork point that appears when the sequential processing program is executed with input data, and removes fork points with a dynamic boost value satisfying a dynamic rounding condition. As a maximum weight independent set problem, the fork point combination determination section obtains an initial combination of fork points, which are not in an exclusive relationship, with the maximum sum of dynamic boost values, and retrieves an optimal combination based on an iterative improvement method.

Abstract: A program parallelizing apparatus, a program parallelizing method and a program parallelizing program capable of creating a parallelized program of better parallel execution performance at a high speed. A fork point determination section extracts fork points from a sequential processing program. A fork point combination determination section divides sequential execution trace information gathered while the sequential processing program is being executed with particular input data into a plurality of segments, obtains an optimal combination of fork points in each information segment from a set of fork points that appear in the information segment, and integrates the optimal combinations of fork points in the respective information segments according to an appropriate criterion to generate one optimal fork point combination.

Abstract: A program parallelizing apparatus, a program parallelizing method and a program parallelizing program capable of creating a parallelized program of higher parallel execution performance. A fork point determination section converts an instruction sequence in part of an input sequential processing program into another instruction sequence to produce at least one sequential processing program. With respect to each of the input sequential processing program and the one or more programs obtained by the conversion, the fork point determination section obtains a set of fork points and an index of parallel execution performance to select a sequential processing program for parallelization and a fork point set with the best parallel execution performance index. A fork point combination determination section determines an optimal combination of fork points included in the fork point set determined by the fork point determination section.

Abstract: When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning success/failure results of the speculative execution of memory operation instructions of the past is referred to and thereby whether the speculative execution will succeed or fail is predicted. In the prediction, the target address of the memory operation instruction is converted by a hash function circuit into an entry number of the speculative execution result history table (allowing the existence of aliases), and an entry of the table designated by the entry number is referred to. If the prediction is “success”, the memory operation instruction is executed in out-of-order execution speculatively (with regard to data dependence relationship between the instructions).

Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: The processors #0 to #3 execute a plurality of threads whose execution sequence is defined, in parallel. When the processor #1 that executes a thread updates the self-cache memory #1, if the data of the same address exists in the cache memory #2 of the processor #2 that executes a child thread, it updates the cache memory #2 simultaneously, but even if it exists in the cache memory #0 of the processor #0 that executes a parent thread, it doesn't rewrite the cache memory #0 but only records that rewriting has been performed in the cache memory #1. When the processor #0 completes a thread, a cache line with the effect that the data has been rewritten recorded from a child thread may be invalid and a cache line without such record is judged to be effective. Whether a cache line which may be invalid is really invalid or effective is examined during execution of the next thread.

Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: A facsimile system includes a facsimile machine reading image data from an original, a computer transmitting to and receiving from the facsimile machine data of addressee identification information indicative of at least a name of addressee and a facsimile number corresponding to the name of addressee, a computer-side storage circuit provided at a computer side for storing the data of addressee identification information, a computer-side referring circuit provided at the computer side for referring to the data of addressee identification information stored in the computer-side storage circuit, and an instruction circuit provided in the facsimile machine so as to be instructed at a facsimile machine side to refer via the computer-side referring circuit to the data of addressee identification information stored in the computer-side storage circuit.

Abstract: In a parallel processor system for executing a plurality of threads which are obtained by dividing a single program in parallel each other by a plurality of processors, when a processor executing a master thread conducts forking of a slave thread in other processor, at every write to a general register in the master thread after forking, the fork source processor transmits an updated register value to the fork destination processor through a communication bus. The fork destination processor executes the slave thread for speculation and upon detecting an offense against Read After Write (RAW) related to the general register, cancels the thread being executed to conduct re-execution of the thread.

Abstract: A computer system includes a first heat generating element in which a heat generation amount is changed, a second heat generating element, a fan configured to cool the first and second heat generating elements, a first temperature sensor configured to detect a temperature of the first heat generating element, a second temperature sensor configured to detect a temperature of the second heat generating element, and a controller configured to control a rotation speed of the cooling fan, based on the temperatures detected by the first and second temperature sensors.

Abstract: A facsimile system includes a facsimile machine reading image data from an original, a computer transmitting to and receiving from the facsimile machine data of addressee identification information indicative of at least a name of addressee and a facsimile number corresponding to the name of addressee, a computer-side storage circuit provided at a computer side for storing the data of addressee identification information, a computer-side referring circuit provided at the computer side for referring to the data of addressee identification information stored in the computer-side storage circuit, and an instruction circuit provided in the facsimile machine so as to be instructed at a facsimile machine side to refer via the computer-side referring circuit to the data of addressee identification information stored in the computer-side storage circuit.

Abstract: An internet facsimile machine capable of facsimile transmission via an internet to an addressee includes an identification information input circuit for inputting user identification information of an address of an addressee, a predetermined information input/selection circuit for inputting or selecting a predetermined piece of information so that information relating to a user in the address of the addressee is narrowed, a storage unit for storing a large amount of information about the user, a candidate presenting circuit for presenting a candidate for information relating to the user in the address of the addressee by relating the predetermined information input or selected by the input/selection circuit to the information about the user stored in the storage unit, a presented candidate determining circuit for determining only one candidate when said one candidate is presented by the candidate presenting circuit, and for selecting and determining either or any one of two or more candidates when said two or

Abstract: A control/data flow analysis unit analyzes the control flow and the data flow of a sequential processing program, and a fork point candidate determination unit determines fork point candidates taking this as the reference. A best fork point candidate combination determination unit determines the best fork point candidate combination by taking as the reference the result from the evaluation of the parallel execution performance of a test fork point candidate combination by a parallel execution performance evaluation unit, and a parallelized program output unit generates and outputs a parallelized program by inserting a fork command based on the best fork point candidate combination.

Abstract: The invention provides a image duplicating apparatus capable of forming images for duplication using standard four ink colors in a standard color style, or using more ink colors than the standard ink colors when duplicating images read from an original on a recording paper. A CPU determines which of the single-copying mode, where images read from the original are duplicated on a sheet of the recording paper, or the multi-copying mode, where images read from the original are duplicated on the sheets of the recording paper, is set. When it is determined that the multi-copying mode is set, the CPU starts duplicating in the standard color style. When it is determined that the single-copying mode is set, the CPU starts duplicating in the fine color style.