Patents by Inventor Satoshi Mitsugi
Satoshi Mitsugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250069215Abstract: According to one embodiment, an evaluation method including: applying a first transform processing on a first two-dimensional data and a second two-dimensional data to generate a first spectrum and a second spectrum respectively, the first two-dimensional data indicating a defect distribution of a first substrate on which a pattern is formed by imprinting an original mold onto a photoresist on the first substrate, the second two-dimensional data indicating a predicted defect distribution of a second substrate; filtering the generated first spectrum and the generated second spectrum; applying a second transform processing to the processed first spectrum and the processed second spectrum to restore the first two-dimensional data and the second two-dimensional data, respectively; applying thresholding on the restored first two-dimensional data and the restored second two-dimensional data, respectively; and calculating a matching degree by applying a comparison function to the thresholded first two-dimensional daType: ApplicationFiled: August 21, 2024Publication date: February 27, 2025Applicant: Kioxia CorporationInventor: Satoshi MITSUGI
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Publication number: 20240316915Abstract: A pattern design method according to an embodiment is a method to design a pattern of a template used for an imprint process. The imprint process serves to form a predetermined pattern by pressing a shot surface of the template against a surface of a processed layer. The method includes setting an outer edge coverage range corresponding to an outer edge region located a predetermined distance inside an edge of the shot surface of the template. The outer edge coverage range is set to be different from an inner coverage range corresponding to an inner region inside the outer edge region. The method includes designing a pattern in the outer edge region to have a coverage falling within the outer edge coverage range. The method includes designing a pattern in the inner region to have a coverage falling within the inner coverage range.Type: ApplicationFiled: March 7, 2024Publication date: September 26, 2024Applicant: Kioxia CorporationInventors: Sachiko KOBAYASHI, Kazuhiro TAKAHATA, Satoshi MITSUGI
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Patent number: 12078922Abstract: A template of one embodiment includes an alignment mark. The alignment mark includes a first main pattern and a first auxiliary pattern. In the first main pattern, a first part and a second part are disposed according to a predetermined repeating pattern. The first auxiliary pattern is configured as a pattern opposite to the repeating pattern in a region outside an end of the first main pattern.Type: GrantFiled: September 10, 2021Date of Patent: September 3, 2024Assignee: Kioxia CorporationInventors: Takashi Sato, Takeshi Suto, Satoshi Mitsugi
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Patent number: 11815348Abstract: According to one embodiment, a template includes an alignment mark. The alignment mark includes first marks arranged at a first pitch in a first direction and second marks arranged at a second pitch in the first direction. At least one of the first marks includes a first region and a third region. At least one of the second marks includes a second region and the third region. The first region has first patterns arranged in a line-and-space form in the first direction. The second region has second patterns arranged in a line-and-space form in a second direction orthogonal to the first direction.Type: GrantFiled: September 9, 2021Date of Patent: November 14, 2023Assignee: Kioxia CorporationInventors: Takashi Sato, Satoshi Mitsugi
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Publication number: 20230298888Abstract: According to one embodiment, a pattern forming method includes forming a first resin pattern on a substrate with a first resin. The first resin pattern includes a first transfer pattern and a first mark. A second resin is dispensed to cover the first mark of the first resin pattern. A first pattern is formed including the first transfer pattern and the second resin covering the first mark. The first pattern is then transferred to a first process film on the substrate.Type: ApplicationFiled: August 31, 2022Publication date: September 21, 2023Inventor: Satoshi MITSUGI
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Publication number: 20220308440Abstract: A template of one embodiment includes an alignment mark. The alignment mark includes a first main pattern and a first auxiliary pattern. In the first main pattern, a first part and a second part are disposed according to a predetermined repeating pattern. The first auxiliary pattern is configured as a pattern opposite to the repeating pattern in a region outside an end of the first main pattern.Type: ApplicationFiled: September 10, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventors: Takashi SATO, Takeshi SUTO, Satoshi MITSUGI
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Publication number: 20220307826Abstract: According to one embodiment, a template includes an alignment mark. The alignment mark includes first marks arranged at a first pitch in a first direction and second marks arranged at a second pitch in the first direction. At least one of the first marks includes a first region and a third region. At least one of the second marks includes a second region and the third region. The first region has first patterns arranged in a line-and-space form in the first direction. The second region has second patterns arranged in a line-and-space form in a second direction orthogonal to the first direction.Type: ApplicationFiled: September 9, 2021Publication date: September 29, 2022Applicant: Kioxia CorporationInventors: Takashi SATO, Satoshi Mitsugi
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Patent number: 10908519Abstract: In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.Type: GrantFiled: September 11, 2019Date of Patent: February 2, 2021Assignee: Toshiba Memory CorporationInventor: Satoshi Mitsugi
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Publication number: 20200301293Abstract: In an alignment mark of an embodiment, a first pattern includes a first portion and a second portion, a second pattern includes a third portion and a fourth portion, the first portion and the third portion partially overlap each other, the second portion and the fourth portion partially overlap each other, a pitch length of each structural periods of the first portion and the third portion are equal within 1.2 times, a pitch length of each structural periods of the second portion and the fourth portion are equal within 1.2 times, a duty ratio of each of the first and third portions is 1:1, and a duty ratio of the second portion is D:2, and D is an integer of two or more, the duty ratio being a ratio between a light-shielding portion and a light-transmitting portion.Type: ApplicationFiled: September 11, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventor: Satoshi MITSUGI
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Patent number: 10739676Abstract: In an alignment mark of an embodiment, a first pattern has a periodic structure in a first direction on a surface of an original or a surface of a substrate and extends in a second direction, and a second pattern has a periodic structure in a third direction on the surface of the original or the surface of the substrate and extends in a fourth direction. The first direction and the third direction are parallel to each other. A period in the first direction of the periodic structure of the first pattern is equal to a period in the third direction of the periodic structure of the second pattern. At least one of the first pattern and the second pattern has a periodic structure in a fifth direction orthogonal to the first direction and the third direction on the surface of the original or the surface of the substrate. At least one of the second direction and the fourth direction is oblique with respect to the fifth direction.Type: GrantFiled: March 12, 2019Date of Patent: August 11, 2020Assignee: Toshiba Memory CorporationInventor: Satoshi Mitsugi
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Publication number: 20190369488Abstract: In an alignment mark of an embodiment, a first pattern has a periodic structure in a first direction on a surface of an original or a surface of a substrate and extends in a second direction, and a second pattern has a periodic structure in a third direction on the surface of the original or the surface of the substrate and extends in a fourth direction. The first direction and the third direction are parallel to each other. A period in the first direction of the periodic structure of the first pattern is equal to a period in the third direction of the periodic structure of the second pattern. At least one of the first pattern and the second pattern has a periodic structure in a fifth direction orthogonal to the first direction and the third direction on the surface of the original or the surface of the substrate. At least one of the second direction and the fourth direction is oblique with respect to the fifth direction.Type: ApplicationFiled: March 12, 2019Publication date: December 5, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Satoshi Mitsugi
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Patent number: 10290498Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.Type: GrantFiled: March 12, 2018Date of Patent: May 14, 2019Assignee: Toshiba Memory CorporationInventors: Satoshi Mitsugi, Takeshi Suto, Takashi Sato, Yukiyasu Arisawa
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Publication number: 20190080899Abstract: According to an embodiment, a first alignment mark includes a first template-side mark in which a plurality of first portions are arranged with a first period, and a second template-side mark in which a plurality of second portions are arranged with a second period. A second alignment mark includes a first wafer-side mark in which a plurality of third portions are arranged with a third period, and a second wafer-side mark in which a plurality of fourth portions are arranged with a fourth period. The first wafer-side mark and the first template-side mark are configured to be overlaid with each other to constitute a first moire mark. The second wafer-side mark and the second template-side mark are configured to be overlaid with each other to constitute a second moire mark. An average period of the first moire mark and an average period of the second moire mark are different from each other.Type: ApplicationFiled: March 12, 2018Publication date: March 14, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Satoshi MITSUGI, Takeshi SUTO, Takashi SATO, Yukiyasu ARISAWA
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Patent number: 9472712Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.Type: GrantFiled: September 3, 2015Date of Patent: October 18, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Mitsugi, Hiroshi Katsuno
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Publication number: 20160211408Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.Type: ApplicationFiled: September 3, 2015Publication date: July 21, 2016Inventors: Satoshi Mitsugi, Hiroshi Katsuno
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Patent number: 9368682Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body, a first electrode, a second electrode, and a dielectric body part. The stacked structure body includes a first semiconductor layer, having a first portion and a second portion juxtaposed with the first portion, a light emitting layer provided on the second portion, a second semiconductor layer provided on the light emitting layer. The first electrode includes a contact part provided on the first portion and contacting the first layer. The second electrode includes a first part provided on the second semiconductor layer and contacting the second layer, and a second part electrically connected with the first part and including a portion overlapping with the contact part when viewed from the first layer toward the second layer. The dielectric body part is provided between the contact part and the second part.Type: GrantFiled: May 15, 2015Date of Patent: June 14, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshiyuki Oka, Shinya Nunoue
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Patent number: 9337396Abstract: According to one embodiment, a semiconductor light emitting device includes a first metal layer, a second metal layer, a third metal layer, a semiconductor light emitting unit and an insulating unit. The semiconductor light emitting unit is separated from the first metal layer in a first direction. The second metal layer is provided between the first metal layer and the semiconductor light emitting unit to be electrically connected to the first metal layer, and is light-reflective. The second metal layer includes a contact metal portion, and a peripheral metal portion. The third metal layer is light-reflective. The third metal layer includes an inner portion, a middle portion, and an outer portion. The insulating unit includes an first insulating portion, a second insulating portion, and a third insulating portion.Type: GrantFiled: February 6, 2014Date of Patent: May 10, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Katsuno, Satoshi Mitsugi, Toshihide Ito, Shinya Nunoue
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Patent number: 9337385Abstract: A semiconductor light emitting element includes a substrate and a stacked body. The stacked body is aligned with the substrate. The stacked body includes first and second semiconductor layers, a light emitting layer, and first and second electrodes. The first semiconductor layer has a first face including first and second portions. The first portion is provided with a plurality of convex portions. The second portion is aligned with the first portion. The second semiconductor layer is provided facing the second portion. The light emitting layer is provided between the second portion and the second semiconductor layer. The second semiconductor layer is disposed between the second electrode and the light emitting layer. An interval of each of the convex portions is no less than 0.5 times and no more than 4 times a wavelength of a light emitted from the light emitting layer.Type: GrantFiled: July 3, 2014Date of Patent: May 10, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Mitsugi, Shinji Yamada, Shinya Nunoue
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Patent number: 9324917Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting layer, a bonding pad, a narrow wire electrode and a first insulating layer. The light emitting layer is provided between the first semiconductor layer and the second semiconductor layer and is in contact with the first semiconductor layer. The narrow wire electrode includes a first portion and a second portion. The first portion is provided on a surface of the first semiconductor layer not in contact with the light emitting layer and is in ohmic contact with the first semiconductor layer. The second portion is provided on the surface and located between the first portion and the bonding pad. The narrow wire electrode is electrically connected to the bonding pad. The first insulating layer is provided between the second portion and the first semiconductor layer.Type: GrantFiled: August 31, 2012Date of Patent: April 26, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Katsuno, Satoshi Mitsugi, Shinya Nunoue
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Patent number: 9311606Abstract: According to one embodiment, a quantum computer includes a crystal, an optical resonator, and a light source. A host crystal included in the crystal satisfying three conditions a first condition that maximum phonon energy of the host crystal is low, and so that a homogenous broadening of a 3F3(1) level of the Pr3+ ion resulting from relaxation due to phonon emission is smaller than respective hyperfine splits of a 3H4(1) level and the 3F3(1) level of the Pr3+ ion, a second condition that a site of the Pr3+ ion does not have inversion symmetry, and the Pr3+ ion has a Stark level in which the 3H4(1) level and the 3F3(1) level of the Pr3+ ion are not degenerate, and a third condition that each atom in the host crystal has no electronic magnetic moment.Type: GrantFiled: March 12, 2012Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hayato Goto, Satoshi Mitsugi, Kouichi Ichimura