Patents by Inventor Satoshi Nagashima

Satoshi Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11049868
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: June 29, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Nagashima, Tatsuya Kato, Wataru Sakamoto
  • Patent number: 10991713
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: April 27, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Keisuke Nakatsuka, Fumitaka Arai, Shinya Arai, Yasuhiro Uchiyama
  • Patent number: 10985175
    Abstract: A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D1; a distance from surfaces of the stacked bodies facing the semiconductor portion on a predetermined second cross-section being represented by D2, the relationship 2D1>D2 is satisfied.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: April 20, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Satoshi Nagashima
  • Publication number: 20210091112
    Abstract: According to one embodiment, a semiconductor device comprising: a first stacked structure in which first insulating layers and first conductive layers are alternately stacked; a second stacked structure in which second insulating layers and second conductive layers are alternately stacked; a first memory pillar provided in the first stacked structure; a first dividing structure dividing the first conductive layers; a second memory pillar provided within the second stacked structure and connected to the first memory pillar; a second dividing structure dividing the second conductive layers; a first alignment mark pillar provided in the first stacked structure and projecting from the first stacked structure; a second alignment mark pillar provided on the first alignment mark pillar; an alignment mark surrounded by the second alignment mark pillar.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Yumi NAKAJIMA, Satoshi NAGASHIMA
  • Patent number: 10957702
    Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Oga, Hideaki Harakawa, Satoshi Nagashima, Natsuki Fukuda
  • Publication number: 20210036000
    Abstract: A semiconductor memory device includes a first pillar. The first pillar includes a first portion and a second portion. The first portion includes a first semiconductor layer and a first insulating film on a side surface of the first semiconductor layer. The first pillar includes a first region that faces the first portion and a second region other than the first region. The second portion includes a first conductive film that is in contact with the first insulating film and a second insulating film. The second insulating film has a first thickness in a fourth direction within the second region and a second thickness in the second direction within the first region. The first thickness is greater than the second thickness.
    Type: Application
    Filed: March 10, 2020
    Publication date: February 4, 2021
    Applicant: Kioxia Corporation
    Inventors: Naoya YOSHIMURA, Satoshi NAGASHIMA
  • Patent number: 10910388
    Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Satoshi Nagashima, Tetsu Morooka, Noritaka Ishihara
  • Patent number: 10879261
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Fumitaka Arai
  • Publication number: 20200286902
    Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.
    Type: Application
    Filed: July 22, 2019
    Publication date: September 10, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Natsuki FUKUDA, Satoshi NAGASHIMA, Tetsu MOROOKA, Noritaka ISHIHARA
  • Publication number: 20200176809
    Abstract: Present disclosure provides a lithium ion secondary battery element in which a positive electrode including a positive electrode active material layer formed by applying a positive electrode active material mixture, a separator, and a negative electrode including a negative electrode active material layer formed by applying a negative electrode active material mixture are stacked.
    Type: Application
    Filed: June 25, 2018
    Publication date: June 4, 2020
    Applicant: Envision AESC Japan Ltd.
    Inventors: Shin Tanaka, Kenji Ohara, Satoshi Nagashima, Jiro Iriyama
  • Patent number: 10665598
    Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: May 26, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Shinya Arai
  • Patent number: 10636803
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Publication number: 20200098784
    Abstract: According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.
    Type: Application
    Filed: March 8, 2019
    Publication date: March 26, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Fumitaka ARAI
  • Publication number: 20200091181
    Abstract: A semiconductor memory device comprises: stacked bodies adjacent to each other in a second direction, each comprising conductive layers stacked in a first direction; semiconductor portions arranged in a third direction between the stacked bodies, and comprising semiconductor layers facing the conductive layers, and a first insulating layer; and a second insulating layer provided between the semiconductor portions. The smallest distance from a geometrical center of gravity of the second insulating layer to the stacked body on a predetermined first cross-section being represented by D1; a distance from surfaces of the stacked bodies facing the semiconductor portion on a predetermined second cross-section being represented by D2, the relationship 2D1>D2 is satisfied.
    Type: Application
    Filed: March 6, 2019
    Publication date: March 19, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Satoshi NAGASHIMA
  • Publication number: 20200075622
    Abstract: According to one embodiment, a semiconductor memory device includes: a first insulating layer provided between first and second interconnection layers; a first semiconductor layer provided between the first interconnection layer and the first insulating layer; a second semiconductor layer provided between the second interconnection layer and the first insulating layer; a first charge storage layer provided between the first interconnection layer and the first semiconductor layer; a second charge storage layer provided between the second interconnection layer and the second semiconductor layer; and a second insulating layer provided between the first interconnection layer and the second interconnection layer, between the first semiconductor layer and the second semiconductor layer, and between the first charge storage layer and the second charge storage layer.
    Type: Application
    Filed: February 25, 2019
    Publication date: March 5, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kotaro FUJII, Satoshi NAGASHIMA, Yumi NAKAJIMA
  • Publication number: 20200075615
    Abstract: According to an embodiment, a semiconductor memory device includes: a first stacked body including a first semiconductor layer, a first memory film, a second semiconductor layer and a first insulating layer; a joining member provided on the first semiconductor layer, the second semiconductor layer, and the first insulating layer; a first layer provided above the joining member and covering the first semiconductor layer and the first memory film; a second layer provided above the joining member, located away from the first layer as viewed in a second direction perpendicular to the first direction, and covering the second semiconductor layer and the second memory film; a second stacked body including a third semiconductor layer, a fourth semiconductor layer, a fourth memory film and a second insulating layer.
    Type: Application
    Filed: March 7, 2019
    Publication date: March 5, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi OGA, Hideaki HARAKAWA, Satoshi NAGASHIMA, Natsuki FUKUDA
  • Publication number: 20190333928
    Abstract: According to one embodiment, a semiconductor memory device includes: first and second signal lines; a first memory cell storing first information by applying voltage across the first signal line and a first interconnect layer; a second memory cell storing second information by applying voltage across the second signal line and a second interconnect layer; a first conductive layer provided on the first and second signal lines; third and fourth signal lines provided on the first conductive layer; a third memory cell storing third information by applying voltage across the third signal line and a third interconnect layer; and a fourth memory cell storing fourth information by applying voltage across the fourth signal line and a fourth interconnect layer.
    Type: Application
    Filed: March 11, 2019
    Publication date: October 31, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Keisuke NAKATSUKA, Fumitaka ARAI, Shinya ARAI, Yasuhiro UCHIYAMA
  • Publication number: 20190326309
    Abstract: A semiconductor memory device includes a substrate, a plurality of first electrode layers, a semiconductor layer, a plurality of second electrode layers, and a conductor. The plurality of first electrode layers are arranged to be separated from each other in a first direction above the substrate. The semiconductor layer extends through the plurality of first electrode layers in the first direction. The plurality of second electrode layers are arranged to be separated from each other in the first direction, arranged to be separated from the plurality of first electrode layers in a second direction crossing the first direction, and arranged at substantially the same levels as levels of the plurality of first electrode layers in the first direction. The conductor electrically connects the plurality of second electrode layers to each other. The plurality of second electrode layers are connected in parallel by the conductor.
    Type: Application
    Filed: September 12, 2018
    Publication date: October 24, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi NAGASHIMA, Shinya ARAI
  • Publication number: 20190296040
    Abstract: A semiconductor device according to an embodiment includes first conductors, first pillars, a pillar column. Each of the first pillars is provided through the first conductors. The pillar column includes second pillars that are aligned in a first direction. Each of the second pillars is provided through the first conductors. The pillar column includes first and second columns of the second pillars. The first and second columns of the second pillars are aligned in a second direction that intersects the first direction. The first pillars are arranged on both sides in the second direction of each pillar column. The first conductors are provided continuously on both sides in the second direction of the second pillars that are included in each pillar column.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 26, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kotaro FUJII, Masahisa SONODA, Masaru KITO, Satoshi NAGASHIMA, Shigeki KOBAYASHI
  • Patent number: 10418376
    Abstract: A semiconductor memory device according to one embodiment, includes a first electrode film, a plurality of semiconductor members, and a charge storage member. The first electrode film includes three or more first portions and a second portion connecting the first portions to each other. The first portions extend in a first direction and are arranged along a second direction that intersects with the first direction. The plurality of semiconductor members are arranged along the first direction between the first portions and extending in a third direction. The third direction intersects with a plane containing the first direction and the second direction. The charge storage member is disposed between each of the semiconductor members and each of the first portions. The second portion is disposed between the semiconductor members.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koichi Sakata, Yuta Watanabe, Keisuke Kikutani, Satoshi Nagashima, Fumitaka Arai, Toshiyuki Iwamoto