Abstract: Plural first charge accumulation layers are arranged on a first gate-insulating film, and divided in the first direction and the second direction. Plural second charge accumulation layers are arranged on a second gate-insulating film and divided in the first direction and the second direction. An intermediate insulating film is arranged on the side surface of the first charge accumulation layers and on the side surface of the second charge accumulation layers. The control electrode includes a side-surface portion, which is arranged on the side surface of the intermediate insulating film, extends in the second direction, and faces via the intermediate insulating film to the side surface of the first charge accumulation layer and the side surface of the second charge accumulation layer, and a pad portion arranged monolithically on the lower portion of the side-surface portion and having a width larger than the film thickness of the side-surface portion.

Abstract: A semiconductor device includes a memory cell transistor that is formed via a first gate insulating film on an active region of a memory cell region and has a gate electrode including a first charge storage layer, a first interelectrode insulating film, and a first control gate electrode film. A transistor, which includes a second gate insulating film on the active region or a peripheral circuit region and a gate electrode including a second charge storage layer, a second interelectrode insulating film, and a second control gate electrode film, is also provided. A groove with a funnel shape is formed in a trap film of the second charge storage layer, and the second control gate electrode film and the polysilicon film of the second charge storage layer are interconnected via the groove.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].

Abstract: In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed.

Abstract: A hybrid vehicle in which a forced charge area is set where vehicle travel is prohibited and a capacitor is charged by regenerating an electric motor with drive power of an internal combustion engine. The capacitor is charge in accordance with a temperature and charge amount of the capacitor. The forced charge area has a time-limited travel permission area in which predetermined vehicle travel is permitted up to a predetermined permitted amount of time, for vehicle travel using the internal combustion engine as a driving force source, and other vehicle travel during which the capacitor can be efficiently charged is permitted.

Abstract: In a manufacturing method, gate electrode materials and a hard-mask material are deposited above a substrate. First mandrels are formed on the hard-mask material in a region of cell array. A second mandrel is formed on the hard-mask material in a region of a selection gate transistor. First sidewall-masks are formed on side-surfaces of the first mandrels. A second sidewall-mask is formed on a side-surface of the second mandrel. An upper side-surface of the second sidewall-mask is exposed. A sacrificial film is embedded between the first sidewall-masks. A sacrificial spacer is formed on the upper side-surface of the second sidewall-mask. A resist film covers the second mandrel. An outer edge of the resist film is located between the first mandrel closest to the second mandrel and the sacrificial spacer. The first mandrels are removed using the resist film as a mask. And, the sacrificial film and spacer are removed.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A method of manufacturing a nonvolatile semiconductor storage device includes filling an element isolation trench with a sacrificial film; etching a laminate of films to form a plurality of first and second gate electrodes such that the first gate electrodes are disposed in a first region, and the second gate electrodes are disposed in a second region adjacent to the first region; removing the sacrificial film; forming a resist having an opening in the first region; forming a barrier insulating film so as to at least cover an edge of the opening; etching back the barrier insulating film and thereafter removing the resist film; forming an insulating film to form an unfilled gap in the element isolation trench located below the second gate electrode, the second region, and the third region.

Abstract: A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

Abstract: A semiconductor device has 3n, 3n+1, and 3n+2 connector lines that are formed together. The 3n+1 connector line is located between the 3n connector line and the 3n+2 connector line. The first fringe pattern pad is located at the terminus of the 3n connector line and is formed with a wider space than the width of the 3n connector line. The second fringe pattern pad is located at the terminus of the 3n+1 connector line and is formed with a wider width than the width of the 3n+1 connector line. The third fringe pattern pad is located at the terminus of the 3n+2 connector line and is formed with a wider width than the width of the 3n+2 connector line. The second fringe pattern pad is positioned closer to a memory array as compared with the terminus of each connector line with the first and third fringe pattern pads.

Abstract: According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

Abstract: A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed on the semiconductor substrate at predetermined intervals, a selecting transistor arranged on each of two sides of each of the plurality of word lines in which a spacing between the selecting transistor and an adjacent one of the word lines is not less than three times a width of each of the word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and selecting transistors, a first cavity portion which is located between each pair of adjacent ones of the word lines and whose upper portion is covered with the interlayer insulating film, a second cavity portion which is formed at a side wall portion of the word line adjacent to each selecting transistor which faces the selecting transistor and whose upper portion is covered with the interlayer insulating film, and a third cavity portion which is formed at a side wall portion of each of the selecting transistors and whose upper portion

Abstract: A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.

Abstract: According to one embodiment, a plurality of memory cells are provided on a semiconductor substrate. In each memory cell, a control gate electrode is provided on a charge accumulation layer with an inter-electrode insulation film interposed between the control gate electrode and the charge accumulation layer, an air gap is provided between the charge accumulation layers adjacent to each other in a word line direction, and an insulation film disposed below the inter-electrode insulation film is divided into an upper part and a lower part by the air gap.