Patents by Inventor Satoshi Nishikawa
Satoshi Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11175520Abstract: An optical semiconductor device includes a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, and a mesa waveguide provided on the principal surface of the first semiconductor layer. The semiconductor device also includes a buried layer covering the upper surface of the first semiconductor layer. Part of the upper surface of the first semiconductor layer is exposed. A mesa structure provided at the boundary between a part of the first semiconductor layer is covered with the buried layer and a part of the first semiconductor layer is exposed. One side of the mesa structure is covered with the buried layer, and the other side is exposed. The optical semiconductor device can reduce the generation of stress in the buried layer, for example, to suppress the occurrence of cracks in the buried layer and enhance the reliability.Type: GrantFiled: October 2, 2018Date of Patent: November 16, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yuichiro Horiguchi, Satoshi Nishikawa, Koichi Akiyama, Keigo Fukunaga, Yohei Hokama, Yosuke Suzuki
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Patent number: 11143821Abstract: An integrated grating coupler system includes a first chip having a first substrate, a first grating structure formed by first grating curves arranged on the first substrate and a cladding layer formed to cover the first grating structure, wherein the first chip include a first waveguide configured to receive a light beam from a first end via the first waveguide and transmit the light beam through a second end, a second chip having a second substrate and a second grating structure formed by second grating curves arranged on the second substrate, wherein the second chip is configured to receive the light beam from the second end of the first chip and transmit the light beam from an end of the second chip, and a common block configured to mount the first chip and second chip via a first submount and a second submount respectively, wherein the first and second submounts are arranged such that the light beam from the second end of the first chip is received at a top of the second chip.Type: GrantFiled: March 24, 2020Date of Patent: October 12, 2021Assignees: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Jonathan Klamkin
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Publication number: 20210255812Abstract: A management device that manages an image processing device via a network includes a first acquisition unit acquiring application information for each application which is installed in the image processing device; a creation unit creating a task for monitoring an operation of an application in the image processing device; and a second acquisition unit acquiring resource information on resources which are required for using an application in the image processing device in accordance with the created task. An instruction on processing of a second type of application installed in the image processing device is executed when the acquired resource information satisfies predetermined conditions.Type: ApplicationFiled: February 3, 2021Publication date: August 19, 2021Inventor: Satoshi Nishikawa
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Patent number: 11093228Abstract: A management apparatus transmits an installation instruction for installing an application to a target device according to a task created by using a template. In a case where the template used for creating the task is a template for installing the latest version of an application, an instruction for installing the latest version of the application is transmitted to the target device.Type: GrantFiled: June 20, 2019Date of Patent: August 17, 2021Assignee: Canon Kabushiki KaishaInventor: Satoshi Nishikawa
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Patent number: 11079550Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: GrantFiled: January 28, 2020Date of Patent: August 3, 2021Assignee: Mitsubishi Electric Research Laboratories, Inc.Inventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Publication number: 20210181427Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: ApplicationFiled: February 23, 2021Publication date: June 17, 2021Applicants: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Patent number: 10996400Abstract: An optical waveguide interferometer that includes a first optical section, a second optical section, and a set of optical waveguides configured to connect the first and second optical sections, such that light propagating between the first optical section and the second optical section passes through each optical waveguide in the set, wherein the set of optical waveguides includes a first optical waveguide having a first length and a first width and a second optical waveguide having a second length and a second width, wherein the second length is greater than the first length, and the second width is greater than the first width.Type: GrantFiled: August 4, 2016Date of Patent: May 4, 2021Assignees: Mitsubishi Electric Research Laboratories, Inc.Inventors: Keisuke Kojima, Bingnan Wang, Toshiaki Koike-Akino, Koichi Akiyama, Eiji Yagyu, Satoshi Nishikawa, Kosuke Shinohara
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Publication number: 20210116645Abstract: A grating coupler having first and second ends for coupling a light beam to a waveguide of a chip includes a substrate configured to receive the light beam from the first end and transmit the light beam through the second end, the substrate having a first refractive index n1, a grating structure having curved grating lines arranged on the substrate, the grating structure having a second refractive index n1, wherein the curved grating lines have line width w and height d and are arranged by a pitch ?, wherein the second refractive index n2 is less than first refractive index n1, and a cladding layer configured to cover the grating structure, wherein the cladding layer has a third refractive index n3. The curves of the grating lines are constructed such that the emitting beam is shaped for efficient coupling to another optical component. The curves can also be tilted to reduce coupling back into the waveguide.Type: ApplicationFiled: January 28, 2020Publication date: April 22, 2021Applicants: Mitsubishi Electric Research Laboratories, Inc., Mitsubishi Electric CorporationInventors: Keisuke Kojima, Satoshi Nishikawa, Shusaku Hayashi, Yosuke Suzuki, Jonathan Klamkin, Yingheng Tang
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Patent number: 10983272Abstract: A multi-mode interference multiplexer/demultiplexer can suppress reflected return light while guiding light to a single-mode waveguide. The multi-mode interference multiplexer/demultiplexer includes a multi-mode waveguide, a first single-mode waveguide connected to a first end, a second single-mode waveguide opposing the first single-mode waveguide, a third single-mode waveguide connected to a second end, a reflecting surface opposing the third single-mode waveguide, and a fourth single-mode waveguide connected to a side end. Light entering from the second or third single-mode waveguide is reflected off the reflecting surface and forms an image at a first connection on a side end of the fourth single-mode waveguide.Type: GrantFiled: December 4, 2017Date of Patent: April 20, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Masakazu Takabayashi, Satoshi Nishikawa, Koichi Akiyama
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Patent number: 10949142Abstract: An information processing apparatus manages setting information as first setting information. The setting information is necessary to acquire user information from a device through a network. The user information includes at least either one of an upper limit number of storage areas that are allocated in the device and available to a user, or a level of authority to control data to which the user can refer on the device. Setting information which is necessary to acquire the user information from the device is acquired as second setting information. When there is inconsistency between the first and second setting information due to a content mismatch, the user information is acquired from the device through the network by using either one of the first setting information or the second setting information in both the information processing apparatus and the device. The user information acquired from the device is imported.Type: GrantFiled: May 13, 2020Date of Patent: March 16, 2021Assignee: Canon Kabushiki KaishaInventor: Satoshi Nishikawa
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Patent number: 10929273Abstract: A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.Type: GrantFiled: June 13, 2017Date of Patent: February 23, 2021Assignee: HITACHI, LTD.Inventors: Toru Motoya, Masahiro Shiraishi, Satoshi Nishikawa, Keisuke Yamamoto, Tadanobu Toba, Takumi Uezono, Hideo Harada, Yusuke Kanno
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Publication number: 20210044082Abstract: A semiconductor optical integrated device comprises a semiconductor amplifier and a plurality of semiconductor lasers, wherein the semiconductor amplifier and the semiconductor lasers are monolithically integrated on a semiconductor substrate, an n-side cladding layer of the semiconductor amplifier and an n-side cladding layer of each of the semiconductor lasers are electrically insulated by an insulating layer formed between the semiconductor substrate and the n-side cladding layer of the semiconductor lasers and an insulating layer formed between the n-side cladding layer of the semiconductor amplifier and the n-side cladding layer of the semiconductor lasers, the n-side cladding layer of the semiconductor lasers and the p-side cladding layer of the semiconductor amplifier is configured to be electrically connected, and the semiconductor amplifier and each semiconductor laser of the plurality of semiconductor lasers are electrically connected in series.Type: ApplicationFiled: April 23, 2018Publication date: February 11, 2021Applicant: Mitsubishi Electric CorporationInventors: Keisuke MATSUMOTO, Eitaro ISHIMURA, Satoshi KAJIYA, Satoshi NISHIKAWA
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Publication number: 20210025034Abstract: An aluminum alloy suitable for obtaining a die-cast aluminum product having high strength and high toughness, comprises, by mass, Si: 7.0 to 9.0%, Mg: 0.4 to 0.6%, Cu: 0.4 to 0.7%, Cr: 0.5% or less, Mn: 0.5% or less, [Cr+Mn]: 0.1 to 0.8%, Fe: 0.10 to 0.25%, and Sr: 0.005 to 0.02%, the balance being Al and impurities.Type: ApplicationFiled: July 23, 2020Publication date: January 28, 2021Inventor: Satoshi NISHIKAWA
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Patent number: 10892956Abstract: A device management server that manages information regarding an application associated with a product key, and information regarding a panel application includes a first creation unit configured to create a first task for distributing to a network device the application associated with the product key, and a second creation unit configured to create a second task for distributing the panel application to the network device, and in a case where the second task is executed, acquires version information regarding the second application installed on the network device, and distributes a new version of the panel application.Type: GrantFiled: February 4, 2020Date of Patent: January 12, 2021Assignee: Canon Kabushiki KaishaInventor: Satoshi Nishikawa
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Publication number: 20200411827Abstract: An embodiment according to the invention provides a separator for a non-aqueous secondary battery, containing a porous substrate and an adhesive porous layer that contains resin A and resin B1; (1) resin A: a copolymer containing vinylidene fluoride (VDF) and hexafluoropropylene (HFP), in which a molar content of HFP monomer unit with respect to a total molar quantity of VDF monomer unit and HFP monomer unit is from more than 1.5 mol % to 3.5 mol %, and (2) resin B1: a copolymer containing VDF, HFP, and a monomer of formula (1), in which a molar content of HFP monomer unit with respect to a total molar quantity of VDF monomer unit, HFP monomer unit, and a monomer unit of formula (1) is from more than 3.5 mol % to 15 mol % (R1 to R3: H, a halogen atom, a carboxyl group, etc., or a C1-5 alkyl group; X: a single bond, a C1-5 alkylene group, etc., Y: H, a C1-5 alkyl group, etc.Type: ApplicationFiled: November 29, 2018Publication date: December 31, 2020Applicant: Teijin LimitedInventors: Rika KURATANI, Megumi SATO, Satoshi NISHIKAWA
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Publication number: 20200387017Abstract: An optical semiconductor device includes a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, and a mesa waveguide provided on the principal surface of the first semiconductor layer. The semiconductor device also includes a buried layer covering the upper surface of the first semiconductor layer. Part of the upper surface of the first semiconductor layer is exposed. A mesa structure provided at the boundary between a part of the first semiconductor layer is covered with the buried layer and a part of the first semiconductor layer is exposed. One side of the mesa structure is covered with the buried layer, and the other side is exposed. The optical semiconductor device can reduce the generation of stress in the buried layer, for example, to suppress the occurrence of cracks in the buried layer and enhance the reliability.Type: ApplicationFiled: October 2, 2018Publication date: December 10, 2020Applicant: Mitsubishi Electric CorporationInventors: Yuichiro HORIGUCHI, Satoshi NISHIKAWA, Koichi AKIYAMA, Keigo FUKUNAGA, Yohei HOKAMA, Yosuke SUZUKI
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Publication number: 20200364008Abstract: An information processing apparatus manages setting information as first setting information. The setting information is necessary to acquire user information from a device through a network. The user information includes at least either one of an upper limit number of storage areas that are allocated in the device and available to a user, or a level of authority to control data to which the user can refer on the device. Setting information which is necessary to acquire the user information from the device is acquired as second setting information. When there is inconsistency between the first and second setting information due to a content mismatch, the user information is acquired from the device through the network by using either one of the first setting information or the second setting information in both the information processing apparatus and the device. The user information acquired from the device is imported.Type: ApplicationFiled: May 13, 2020Publication date: November 19, 2020Inventor: Satoshi Nishikawa
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Publication number: 20200343511Abstract: Provided is a separator for a non-aqueous secondary battery containing a porous substrate; and a heat resistant porous layer that is provided on one side or on both sides of the porous substrate, and that contains a binder resin and barium sulfate particles, in which an average primary particle size of the barium sulfate particles contained in the heat resistant porous layer is from 0.01 ?m to less than 0.30 ?m.Type: ApplicationFiled: September 18, 2018Publication date: October 29, 2020Applicant: TEIJIN LIMITEDInventors: Yu NAGAO, Megumi SATO, Rika KURATANI, Masato OKAZAKI, Satoshi NISHIKAWA
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Publication number: 20200333992Abstract: A function of a device is displayed as a first display on a client device, and local user authentication information is displayed as a second display according to the function of the device selected on the first display on the client device.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventor: Satoshi Nishikawa
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Patent number: 10811657Abstract: There is provided a separator for a non-aqueous secondary battery, containing a porous substrate, and an adhesive porous layer that is provided on one side or both sides of the porous substrate, in which the adhesive porous layer contains a polyvinylidene fluoride type resin A including a vinylidene fluoride monomer unit and a hexafluoropropylene monomer unit, and a polyvinylidene fluoride type resin B including a vinylidene fluoride monomer unit and a hexafluoropropylene monomer unit, a proportion of the hexafluoropropylene monomer unit in the polyvinylidene fluoride type resin A is more than 1.Type: GrantFiled: November 8, 2016Date of Patent: October 20, 2020Assignee: TEIJIN LIMITEDInventors: Susumu Honda, Satoshi Nishikawa, Takashi Yoshitomi