Abstract: A heart beat/respiration measuring device comprising a sheet-like capacitance-type pressure sensor adapted to be pressed against the human body, and a measuring circuit for measuring a heart rate and/or respiration rate from the output of the sensor. The capacitance-type pressure sensor includes a sheet-like dielectric body elastically deformable in all directions and a pair of conductive clothes with stretchability disposed on opposite sides of the dielectric body. The measuring circuit comprises a resonant circuit wherein the capacitance-type pressure sensor serves as an oscillation capacitor, and a calculation processing circuit for detecting variations in the oscillation frequency of the resonant circuit and calculating the heart rate and/or respiration rate based on the frequency component or components of heart beats and/or respiration included in the variations.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: A liquid ejecting head is adapted to eject liquid toward a target medium. A transporter is adapted to transport a tray on which the target medium is mounted toward a region facing the liquid ejecting head via a transporting path. A tray guide is disposed in a front side of the liquid ejecting apparatus, and having a supporting face adapted to support the tray thereon. The tray guide is movable between a first position connecting the supporting face with the transporting path to allow the transporter to transport the tray to the transporting path and a second position escaping the supporting face from the transporting path. The supporting face is kept being parallel to the transporting path when the tray guide is moved between the first position and the second position.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: A linear solenoid valve includes a solenoid having a coil wound around a coil bobbin, a fixed core, and a movable core for being attracted to the fixed core when the coil is energized, and a valve mechanism having a valve element for selectively bringing an inlet port and an outlet port into and out of fluid communication with each other responsive to a displacement of the movable core. The movable core has a nonmagnetic layer formed on an outer surface thereof and having a predetermined thickness.

Abstract: A bottom of a housing has a protruding support extending a predetermined distance toward a movable core, and the movable core has an annular boss extending a predetermined distance toward the housing. The annular boss is disposed in an annular space defined between the bottom of the housing and the protruding support of the housing.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Abstract: An electrically programmable and erasable non-volatile semiconductor memory such as a flash memory is designed into a configuration in which, when a cutoff of the power supply occurs in the course of a write or erase operation carried out on a memory cell employed in the non-volatile semiconductor memory, the operation currently being executed is discontinued and a write-back operation is carried out to change a threshold voltage of the memory cell in the reversed direction. In addition, the configuration also allows the number of charge-pump stages in an internal power-supply configuration to be changed in accordance with the level of a power-supply voltage so as to make the write-back operation correctly executable. As a result, no memory cells are put in deplete state even in the event of a power-supply cutoff in the course of a write or erase operation.

Abstract: [Object] To provide an image forming apparatus and image forming method that can prevent a decrease in image quality by preventing a step-out of a driving source, which occurs because a load of a feeding device is applied when a medium is transported for image formation. [Solving Means] When no roller reset operation, by which a paper feed roller is returned to a reset position, is performed (YES in S21), it is judged whether a counted value N of a counter, which indicates a position of a sheet of paper, is below a threshold value Na, which indicates that it is in an A region in which a load of a hopper or paper return levers of an automatic sheet feeder (ASF) is applied to a stepping motor (S22). When N<Na, driving for high torque is selected (S23), and then paper transport in the A region is performed with a high torque (S25). On the other hand, when N?Na, driving for low torque is selected (S24) and then paper transport in a B region after the A region has passed is performed with a low torque (S25).

Abstract: A linear solenoid valve includes a solenoid having a coil wound around a coil bobbin, a fixed core, and a movable core for being attracted to the fixed core when the coil is energized, and a valve mechanism having a valve element for selectively bringing an inlet port and an outlet port into and out of fluid communication with each other responsive to a displacement of the movable core. The movable core has a nonmagnetic layer formed on an outer surface thereof and having a predetermined thickness.

Abstract: The present invention provides a snore detection device comprising a pressure sensor for detecting vibration generated by the human body with respiration, a sound sensor for detecting sound generated by the human body with respiration, and a judging circuit for judging the occurrence of snoring based on output signals of the two sensors. The judging circuit detects a peak occurrence time in variations generated by the output signal of the pressure sensor and a peak occurrence time in variations generated by the output signal of the sound sensor, to judge whether snoring occurs based on the peak occurrence times, respectively, of vibration and sound.

Abstract: In order to manufacture a discharging roller which discharges a recording medium from a recording apparatus, there are a first die formed with a first recess extending in an axial direction of a shaft portion of the discharging roller, and a second die formed with a second recess extending in the axial direction. The first die and the second die are combined such that the first recess and the second recess face to form a continuous cavity. Synthetic resin is injected into the cavity to mold a bore portion of the shaft portion.

Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Abstract: An object of the present invention is to provide a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block, a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliably operation.

Abstract: A linear solenoid valve includes a solenoid having a coil wound around a coil bobbin, a fixed core, and a movable core for being attracted to the fixed core when the coil is energized, and a valve mechanism having a valve element for selectively bringing an inlet port and an outlet port into and out of fluid communication with each other responsive to a displacement of the movable core. The movable core has a nonmagnetic layer formed on an outer surface thereof and having a predetermined thickness.

Abstract: A nonvolatile memory includes circuits each having first control transistors, memory transistors, second control transistors and memory transistors repeatedly connected in series in sequence. Inversion layers are formed in the direction intersecting the serial direction with turning on of the control transistors. A selection circuit selects a connection of the inversion layer placed under the first control transistor and its corresponding read/write circuit. The control transistors placed on both sides adjacent to the memory transistor are turned on to perform reading. The first control transistors placed on both sides of the second control transistor as viewed from side to side are turned on to perform writing into the other of the right and left memory transistors via one of the right and left memory transistors. The selection circuit connects the read/write circuit and the inversion layer in such a manner that the same read/write circuit is used in reading and writing for the same memory transistor.

Abstract: A nonvolatile memory apparatus which need not compare an access address with a faulty address every time for rescuing from any fault is to be provided. The apparatus has memory arrays, data registers for inputting and outputting data to and from the memory arrays, and control circuits. The control circuits, after transferring a plurality of sets of data from the memory arrays to the data registers in response to an instruction to read data, take out rescuing data out of the plurality of sets of data transferred to the data registers, and perform processing to replace with the taken-out rescuing data corresponding faulty addresses on the data register to enable the data on the data register to be supplied to the outside. When any faulty data in the read data are to be replaced with rescuing data on any data register to which data have been transferred from any memory array, read access addresses need not be checked whether or not they are faulty every time an access address is supplied from outside.

Abstract: To provide a technique which enables a load on a controller to be reduced by rapidly detecting n-bit errors during writing/erasing on a chip in ECC in a nonvolatile memory. A flash memory of the present invention, which is a nonvolatile memory that includes plural electrically erasable and writable nonvolatile memory cells and performs write-and-verify processing in a write operation on the nonvolatile memory cells, includes an ECC determination circuit that counts the number of bits of write error detected in the write-and-verify processing, and outputs the information, and a status register for holding pass/fail information of the write operation and the information about the number of bits of write error outputted from the ECC determination circuit.

Abstract: The present invention provides a semiconductor memory device capable of preventing a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitch of word lines at an end of a memory block. Plural dummy word lines are disposed at an end of a memory block and a word driver is mounted for the dummy word line to control the threshold voltage of a dummy memory cell formed below the dummy word line. Also at the time of operating a memory area for storing data from the outside, a bias is applied to the dummy word line. The invention can prevent a defect caused by falling of a word line and deterioration in patterning precision due to disturbance of the pitches of word lines at an end of a memory block, and realize high yield and reliable operation.