Abstract: A parts distributing method for distributing parts to mounting units in a parts mounting system having a plurality of mounting units. The method involves specifying parts of specific kinds which can be mounted with each mounting unit as division-specified parts; distributing parts specified for a specific mounting unit to the specific mounting unit; repeating operations to distribute parts having a maximum mounting time, out of remaining parts other than the division-specified parts, to mounting units which sequentially have a minimum mounting time; and repeating operations to distribute the division-specified parts one by one to mounting units which sequentially have a minimum mounting time.

Abstract: A ring oscillator is formed by connecting three or more odd gate circuits in a ring. Each gate circuit includes a precharge dynamic gate. An output signal from the precharge dynamic gate of one gate circuit is used to precharge the precharge dynamic gates of all the remaining gate circuits. In measuring the gate delay time of the ring oscillator formed by connecting, in a ring, three or more odd gate circuits each including a precharge dynamic gate, the oscillation frequency of the ring oscillator is measured, and the reciprocal of the oscillation frequency is divided by the number of gate circuits constituting the ring oscillator.

Abstract: A dynamic circuit that prevents a malfunction, even when the operating temperature is high, including a pre-charging circuit connected between a power source node and a signal wiring, a plurality of discharging circuits being connected between a power source node and a signal wiring, a plurality f discharging circuit connected between the signal wiring and a ground potential respectively and for being selectively turn-ON/OFF controlled, a leakage current detecting circuit for detecting a current corresponding to a leakage current generated between the signal wiring and the ground potential in the turn-OFF state of each discharging circuit, and a leakage current correcting circuit connected between the power source node and the signal wiring and for continuously supplying to the signal wiring a leakage correction current equivalent to a leakage current of the signal wiring corresponding to a detected current of the leakage current detecting circuit during a leakage current correction period.

Abstract: A output circuit of a semiconductor integrated circuit comprises a prebuffer circuit, an output buffer circuit comprising first and second output buffer circuits for receiving the output of said prebuffer circuit, said first output buffer circuit comprising a CMOS inverter having its input terminal connected to the output terminal of said output buffer circuit and its output terminal connected to an output terminal, said second output buffer circuit comprising MOS transistors for electrically charging or discharging said output terminal and capacitances, the output of said prebuffer circuit being supplied to the gates of the MOS transistors through the respective capacitances. Such an output circuit can effectively reduce simultaneous switching noise without deteriorating its load driving capability.

Abstract: This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.

Abstract: An output circuit of a semiconductor integrated circuit includes a plurality of output transistors having different current driving abilities for a load, and a plurality of signal delay means for delaying signals for driving each of the output transistors by different delay times, wherein the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a first delay time is set to be larger than the current driving ability of that one of the plurality of output transistors which is driven by the delay signal of one of the signal delay means which has a second delay time shorter than the first delay time.

Abstract: In an output circuit for use in a semiconductor IC comprising a CMOS transistors constituting an output buffer, a transfer gate of CMOS structure is connected between the gates of the CMOS transistors as a resistive element. The transfer gate reduces the changes in the gate potentials of output transistors, which occur when logic inputs are supplied to the gates of the output control transistors. Hence, the deformation of the output waveform, which has resulted from the through currents flowing through the output transistors, is minimized.

Abstract: An output circuit includes a plurality of output buffer circuits and a plurality of pre-buffer circuits connected to drive the output buffer circuits. Some of the pre-buffer circuits are each constituted by P- and N-channel MOS transistors having channel widths or channel lengths which are large enough to drive the output buffer circuits, and the remaining pre-buffer circuits are each constituted by P- and N-channel MOS transistors whose channel widths and channel lengths are so determined as to set the current driving ability thereof sufficiently smaller than that of the corresponding output buffer circuits.