Patents by Inventor Satoshi Shibata

Satoshi Shibata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070137215
    Abstract: A cogeneration system is provided which is capable of reliably switching a bypass damper even if a supply of electric power is shut off in an abnormal state etc. and which is unlikely to leak exhaust gas and is cost-effective even if it is increased in size. To this end, an exhaust gas path (10) for introducing exhaust gas from a gas turbine (2) into an exhaust-heat-recovery heat exchanger (8) is provided with a bypass path (11) and an inlet of the bypass path (11) is provided with a bypass damper (12) which is controlled so as to be opened and closed by an air cylinder driven by compressed air from the compressor (3).
    Type: Application
    Filed: February 6, 2004
    Publication date: June 21, 2007
    Applicant: TAKUMA CO., LTD.
    Inventors: Hiroyuki Kishida, Mamoru Shiragaki, Satoshi Shibata
  • Patent number: 7233563
    Abstract: A polarizing optical element changes its optical reflectance and/or transmittance according to a polarization state of incoming light. The optical element includes: a first grating layer including multiple striped portions that extend in a predetermined direction; and a second grating layer including multiple striped portions that extend in that predetermined direction. Average grating pitches of the first and second grating layers are both defined to be shorter than the wavelength of the incoming light. The first grating layer is made of a first material that exhibits a light reflecting property to the incoming light. The second grating layer is made of a second material that reduces the reflection of the incoming light from the first grating layer.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: June 19, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shun Ueki, Tokio Taguchi, Satoshi Shibata, Kiyoshi Minoura, Masahiro Shimizu
  • Publication number: 20070122578
    Abstract: It is an object of the invention to obtain a multilayered molten resin mass capable of providing a multilayered compression-molded product in which the layers of the multilayered compression-molded product are distributed uniformly in the circumferential direction with the intermediate resin layer positioned entirely within the inner and outer resin layers.
    Type: Application
    Filed: October 20, 2004
    Publication date: May 31, 2007
    Applicant: TOYO SEIKAN KAISHA, LTD.
    Inventors: Kazunobu Watanabe, Makoto Etoh, Hotaka Fukabori, Norihisa Hirota, Satoshi Shibata, Tsuneo Imatani
  • Publication number: 20070054444
    Abstract: An amorphous layer 101 is formed in a region from a surface of a silicon substrate 100 to a first depth A. At this time, defects 103 are generated near an amorphous-crystal interface 102. By heat treatment, the crystal structure of the amorphous layer 101 is restored in a region from the first depth A to a second depth B that is shallower than the first depth A. The resultant amorphous layer 101 extends from the surface of the silicon substrate 100 to the second depth B. The defects 103 remain at the first depth A. By ion implantation, a pn junction 104 is formed at a third depth C that is shallower than the second depth B.
    Type: Application
    Filed: March 29, 2005
    Publication date: March 8, 2007
    Inventor: Satoshi Shibata
  • Publication number: 20070048918
    Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
    Type: Application
    Filed: October 26, 2006
    Publication date: March 1, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
  • Patent number: 7103271
    Abstract: A light irradiation heat treatment apparatus and method may use a plane-shaped light irradiation heating component, facing one surface of a workpiece supported in a furnace, to raise the temperature of the workpiece. The temperature of the workpiece is raised by setting an intensity distribution for light irradiated from the light irradiation heating component in accordance with the resistivity of the workpiece. Thereafter, the workpiece is irradiated with light having the set light intensity distribution to raise its temperature.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: September 5, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Emi Kanazaki, Satoshi Shibata, Fumitoshi Kawase
  • Publication number: 20060186354
    Abstract: In this invention, a wafer is placed and kept in the low-temperature region at the bottom of a temperature space that is in a state of radiation equilibrium and that is formed inside chamber by a heating unit. The substrate temperature is gradually raised to 750 deg C. to 800 deg C. Next, the wafer is placed and kept in the high-temperature region in the temperature space and the substrate temperature is raised to the thermal processing temperature. Then thermal processing is performed for a specified period of time. By doing this, it is possible to perform uniform thermal processing without depending on the state of the wafer (ratio of an area covered by silicon nitride film or polysilicon film).
    Type: Application
    Filed: February 14, 2006
    Publication date: August 24, 2006
    Inventors: Fumitoshi Kawase, Satoshi Shibata
  • Patent number: 7046477
    Abstract: A main controller, such as a CPU, causes a runout detector to relearn a runout component using as an initial value a learned value for a runout component of a disk runout that may occur as a disk rotates, the learned value being acquired during manufacture of a disk drive. The learned value for the runout component used as the initial value is saved to a nonvolatile storage device. The main controller calculates a disk shift amount on the basis of a runout component obtained through relearning (that is, a relearned value) and the learned value acquired during the manufacture of the disk drive and used as the initial value.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: May 16, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Shibata
  • Patent number: 7037733
    Abstract: When the emissivity ? on the reverse face of a substrate 10 is measured during annealing processing for the substrate 10, films made from a material that varies the emissivity ?, such as a first DPS film 15 used for forming a plug 15A, a second DPS film 17 used for forming a capacitor lower electrode 17A and a third DPS film 20 used for forming a capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, no film made from a material that varies the emissivity ?, such as a DPS film, is formed on the reverse face of the substrate 10.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: May 2, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Junji Hirase, Tatsuo Sugiyama, Emi Kanasaki, Fumitoshi Kawase, Yasushi Naito
  • Publication number: 20060079044
    Abstract: In a method for fabricating an electronic device including a transistor with a drain extension structure, a correspondence between a size of a gate electrode of the transistor and ion implantation conditions or heat treatment conditions for forming the drain extension structure is previously obtained. This correspondence satisfies that the transistor has a given threshold voltage. After formation of the gate electrode and measurement of the size of the gate electrode, ion implantation conditions or heat treatment conditions for forming the drain extension structure are set based on the previously-obtained correspondence and the measured size of the gate electrode. Ion implantation or heat treatment for forming the drain extension structure is performed under the ion implantation conditions or heat treatment conditions that have been set.
    Type: Application
    Filed: October 4, 2005
    Publication date: April 13, 2006
    Inventors: Satoshi Shibata, Fumitoshi Kawase, Hisako Kamiyanagi, Emi Kanazaki
  • Publication number: 20050236762
    Abstract: A sheet dryer includes sprockets and a delivery chain, at least one heat-resistant glass plate, at least one lower-surface drying lamp, a guide plate, a plurality of first discharge holes, and a plurality of second discharge holes. The sprockets and delivery chain convey a paper sheet along a convey path. The heat-resistant glass plate is arranged under the sheet convey path. The lower-surface drying lamp is arranged under the heat-resistant glass plate and dries the lower surface of the printed/coated paper sheet. The guide plate is arranged adjacent to the heat-resistant glass plate in a sheet convey direction. The first discharge holes are formed in the heat-resistant glass plate. Air is discharged upward through the first discharge holes. The second discharge holes are formed in the guide plate. Air is discharged through the second discharge holes in the widthwise direction of the paper sheet.
    Type: Application
    Filed: April 14, 2005
    Publication date: October 27, 2005
    Inventors: Tomoyuki Hayasaka, Satoshi Shibata
  • Publication number: 20050173386
    Abstract: A distribution is given to a light irradiation intensity at a temperature rise process after starting a light irradiation (open loop control process), and temperature variation of the workpiece is reduced, so that thermal stress applied to a workpiece is reduced. A light irradiation heat treatment method for supporting a workpiece in a furnace, and heat-treating the workpiece by means of plane-shaped light irradiation heating means provided so as to face to one surface of the workpiece includes a process for irradiating a light having a flat intensity distribution to the workpiece from the light irradiation heating means and raising the temperature of the workpiece. In the open loop control process after starting the light irradiation, the temperature variation of the workpiece can be reduced by setting the light irradiation intensity for every plurality of areas.
    Type: Application
    Filed: December 1, 2004
    Publication date: August 11, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Emi Kanazaki, Satoshi Shibata, Fumitoshi Kawase
  • Publication number: 20050140036
    Abstract: A biaxially oriented polyester container with a uniformly and sufficiently elongated and thin-walled bottom part having excellent drop strength, improved ESC resistance and reduced weight, and a method of manufacturing the container. The biaxially oriented polyester container of the present invention is characterized in that, when an X-ray diffraction measurement is performed in and near a bottom center area of the biaxially oriented polyester container formed by a double-stage orientation blow molding method, a peak indicative of molecular orientation is observed near a diffraction angle of 2?=15 to 30° and an orientation parameter (BO) expressed by the following formula (1) is in the range of 0.
    Type: Application
    Filed: August 19, 2003
    Publication date: June 30, 2005
    Inventors: Norihisa Hirota, Satoshi Shibata
  • Publication number: 20050128635
    Abstract: A main controller, such as a CPU, causes a runout detector to relearn a runout component using as an initial value a learned value for a runout component of a disk runout that may occur as a disk rotates, the learned value being acquired during manufacture of a disk drive. The learned value for the runout component used as the initial value is saved to a nonvolatile storage device. The main controller calculates a disk shift amount on the basis of a runout component obtained through relearning (that is, a relearned value) and the learned value acquired during the manufacture of the disk drive and used as the initial value.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 16, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Satoshi Shibata
  • Publication number: 20050123699
    Abstract: A heat-resistant polyester container wherein the temperature T is not lower than 120° C. at a moment when the rate of contraction in the barrel portion of the polyester container represented by the following formula is 0.66%, Ratio of contraction (%)=(amount of contraction/gauge length)×100??(1) wherein the amount of contraction is measured from a test piece cut from the barrel portion of the polyester container so as to possess a gauge length of 20 mm in compliance with TMA without pre-loading while elevating the temperature at a rate of 3° C./min after 30° C. is exceeded. The polyester container exhibits excellent heat resistance, and enables the retort-sterilization to be executed after the food or beverage has been filled and sealed without permitting the barrel portion of the container to be deformed.
    Type: Application
    Filed: April 4, 2003
    Publication date: June 9, 2005
    Inventors: Norihisa Hirota, Satoshi Shibata
  • Patent number: 6891693
    Abstract: A memory section stores values of the runout component, which are obtained in respective predetermined radial positions on the disk. A determining section selects, from the memory section, a value of the runout component corresponding to a target position. A runout detector uses, as an initial value for adaptive learning, the value of the runout component selected by the determining section, and calculates, by the adaptive learning, a value of the runout component contained in a position error between a head position and the target position. A feedforward controller calculates a feedforward value used to suppress the runout component calculated by the runout detector. A feedback controller calculates a feedback value from the position error. An adder generates, from the feedback value and the feedforward value, a control amount used to position the head in the target position.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: May 10, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satoshi Shibata
  • Publication number: 20040264350
    Abstract: A polarizing optical element changes its optical reflectance and/or transmittance according to a polarization state of incoming light. The optical element includes: a first grating layer including multiple striped portions that extend in a predetermined direction; and a second grating layer including multiple striped portions that extend in that predetermined direction. Average grating pitches of the first and second grating layers are both defined to be shorter than the wavelength of the incoming light. The first grating layer is made of a first material that exhibits a light reflecting property to the incoming light. The second grating layer is made of a second material that reduces the reflection of the incoming light from the first grating layer.
    Type: Application
    Filed: June 15, 2004
    Publication date: December 30, 2004
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Shun Ueki, Tokio Taguchi, Satoshi Shibata, Kiyoshi Minoura, Masahiro Shimizu
  • Patent number: 6799888
    Abstract: A test wafer for use in wafer temperature prediction is prepared. The test wafer includes: first semiconductor layer formed in a crystalline state; second semiconductor layer formed in an amorphous state on the first semiconductor layer; and light absorption film formed over the second semiconductor layer. Next, the test wafer is loaded into a lamp heating system and then irradiating the test wafer with a light emitted from the lamp, thereby heating the second semiconductor layer through the light absorption film. Thereafter, a recovery rate, at which a part of the second semiconductor layer recovers from the amorphous state to the crystalline state at the interface with the first semiconductor layer, is calculated. Then, a temperature of the test wafer that has been irradiated with the light is measured according to a relationship between the recovery rate and a temperature corresponding to the recovery rate.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Shibata, Yuko Nambu
  • Publication number: 20040190075
    Abstract: A communication apparatus includes: a communication unit that communicates with other communication apparatus via a communication network; a detector that detects a communicatio status of the communication unit during a period of time at least from a time when a call is issued to the other communication apparatus by the communication apparatus until a time when a response from the other communication apparatus to the call is received by the communication apparatus; a light emitting device configured to emit light in a plurality of light emitting states that are visually discernible; and a controller that controls the light emitting state of the light emitting device in accordance with the communication status detected by the detector.
    Type: Application
    Filed: March 29, 2004
    Publication date: September 30, 2004
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventor: Satoshi Shibata
  • Patent number: 6798434
    Abstract: A facsimile machine includes a detachable ribbon cassette accommodating an ink ribbon and having an EEPROM that stores the amount of the ink ribbon consumed. In the facsimile machine, printing is performed while the ink ribbon is taken up by a take-up motor and the memory contents in the EEPROM are renewed according to the progress of printing. The facsimile machine further includes a ribbon-empty detector that detects that the facsimile machine runs out of the ink ribbon, and a CPU that resets the memory contents in the EEPROM of the ribbon cassette.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 28, 2004
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Satoshi Shibata, Mutsuo Fukuoka