Patents by Inventor Satoshi Shigematsu

Satoshi Shigematsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6060756
    Abstract: A surface shape recognition sensor of this invention includes at least a plurality of capacitance detection elements having sensor electrodes arranged in the same plane on an interlevel dielectric film formed on a semiconductor substrate to be insulated/isolated from each other, capacitance detection means for detecting the capacitances of the capacitance detection elements, and a stationary electrode disposed on the interlevel dielectric film to be insulated/isolated from the sensor electrodes. When an object to be recognized touches the upper surface of the stationary electrode, the capacitances detected by the capacitance detection elements change in accordance with the recesses/projections on the upper surface.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: May 9, 2000
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Katsuyuki Machida, Satoshi Shigematsu, Hiroki Morimura, Akihiko Hirata
  • Patent number: 5473571
    Abstract: A data hold circuit storing a logic state of a predetermined node of a logic circuit immediately before power supply to the logic circuit is interrupted, and restoring the stored logic state to the predetermined node immediately after the power supply is restarted. The data hold circuit includes a memory circuit storing the logic state of the node, a switch circuit connected between the memory circuit and the node, and a control circuit controlling the on/off operation of the switch circuit. The control circuit turns on the switch circuit for a predetermined time period when the power supply is changed from on to off, or from off to on. The memory circuit is continuously supplied with power from a power supply other than that for the logic circuit. While the power supply to the logic circuit is in a steady state either in the power on state or power off state, the switch circuit is kept off, thereby preventing effect of the memory circuit on the logic circuit.
    Type: Grant
    Filed: September 29, 1994
    Date of Patent: December 5, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya