Patents by Inventor Satoshi Shiraki
Satoshi Shiraki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20080231340Abstract: A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.Type: ApplicationFiled: March 19, 2008Publication date: September 25, 2008Applicant: DENSO CORPORATIONInventors: Satoshi Shiraki, Hiroyuki Ban, Junichi Nagata
-
Publication number: 20080007920Abstract: A load driving device includes: an output power device for driving a load; a driving IC for controlling the output power device, wherein the driving IC is electrically coupled with the output power device through a wire or a connection member; and a first electrode substrate. The output power device and the driving IC are mounted on the first electrode substrate. In this case, the output power device is controlled with high speed, and a mounting area of the output power device and the driving IC is reduced.Type: ApplicationFiled: May 31, 2007Publication date: January 10, 2008Applicant: DENSO CORPORATIONInventors: Satoshi Shiraki, Akira Yamada, Hiroyuki Ban
-
Patent number: 7223668Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.Type: GrantFiled: September 17, 2004Date of Patent: May 29, 2007Assignee: DENSO COrporationInventors: Ichiro Ito, Satoshi Shiraki
-
Patent number: 7109558Abstract: A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.Type: GrantFiled: June 4, 2002Date of Patent: September 19, 2006Assignee: Denso CorporationInventors: Takashi Nakano, Satoshi Shiraki, Yutaka Fukuda, Nobumasa Ueda, Shoji Miura
-
Publication number: 20050042882Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.Type: ApplicationFiled: September 17, 2004Publication date: February 24, 2005Inventors: Ichiro Ito, Satoshi Shiraki
-
Publication number: 20050001265Abstract: A semiconductor device includes: a semiconductor substrate with a principal plane; a base region disposed on the principal plane; a source region disposed on the principal plane in the base region to be shallower than the base region; a drain region disposed on the principal plane, and spaced to the base region; a trench disposed on the principal plane; a trench gate electrode disposed in the trench through a trench gate insulation film; a planer gate electrode disposed on the principal plane of the semiconductor substrate through a planer gate insulation film; and an impurity diffusion region having high concentration of impurities and disposed in a portion of the base region to be a channel region facing the planer gate electrode.Type: ApplicationFiled: June 10, 2004Publication date: January 6, 2005Inventors: Satoshi Shiraki, Yoshiaki Nakayama, Shoji Mizuno, Takashi Nakano, Akira Yamada
-
Patent number: 6809034Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.Type: GrantFiled: April 24, 2002Date of Patent: October 26, 2004Assignee: Denso CorporationInventors: Ichiro Ito, Satoshi Shiraki, Tomio Yamamoto, Makoto Ohkawa, Atsumi Takahashi, Yasuaki Tsuzuki, Akito Fukui, Toshio Sakakibara, Takayuki Sugisaka
-
Patent number: 6770564Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.Type: GrantFiled: July 28, 1999Date of Patent: August 3, 2004Assignee: Denso CorporationInventors: Ichiro Ito, Satoshi Shiraki, Tomio Yamamoto, Makoto Ohkawa, Atsumi Takahashi, Yasuaki Tsuzuki, Akito Fukui, Toshio Sakakibara, Takayuki Sugisaka
-
Patent number: 6768183Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: GrantFiled: April 19, 2002Date of Patent: July 27, 2004Assignee: Denso CorporationInventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
-
Publication number: 20030218246Abstract: In a semiconductor device, a plurality of bump electrodes are formed for a source pad or a drain pad. The bump electrodes and the source or drain pad are connected with each other through wiring patterns. Thus, the following effect is produced unlike cases where one bump electrode is connected with one source pad or one drain pad through a wiring pattern: An amount of current that passes through each of the bump electrodes can be reduced, so that a breakdown of the bump electrodes is lessened.Type: ApplicationFiled: May 19, 2003Publication date: November 27, 2003Inventors: Hirofumi Abe, Hiroyuki Ban, Yoshinori Arashima, Hirokazu Itakura, Takao Kuroda, Noriyuki Iwamori, Satoshi Shiraki
-
Patent number: 6573144Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: GrantFiled: August 2, 2002Date of Patent: June 3, 2003Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
-
Publication number: 20020190309Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: ApplicationFiled: August 2, 2002Publication date: December 19, 2002Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
-
Publication number: 20020185681Abstract: A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.Type: ApplicationFiled: June 4, 2002Publication date: December 12, 2002Inventors: Takashi Nakano, Satoshi Shiraki, Yutaka Fukuda, Nobumasa Ueda, Shoji Miura
-
Publication number: 20020153592Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: ApplicationFiled: April 19, 2002Publication date: October 24, 2002Inventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
-
Patent number: 6465839Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: GrantFiled: April 6, 2001Date of Patent: October 15, 2002Assignee: Denso CorporationInventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
-
Publication number: 20020115299Abstract: An Al film is formed on a barrier metal covering a thin film resistor to have a first opening. A photo-resist is formed on the Al film and in the opening, and is patterned to have a second opening having an opening area smaller than that of the first opening and open in the first opening to expose the barrier metal therefrom. Then, the barrier metal is etched through the second opening. Because the barrier metal is etched from an inner portion more than the opening end of the first opening, under-cut of the barrier metal is prevented.Type: ApplicationFiled: April 24, 2002Publication date: August 22, 2002Inventors: Ichiro Ito, Satoshi Shiraki, Tomio Yamamoto, Makoto Ohkawa, Atsumi Takahashi, Yasuaki Tsuzuki, Akito Fukui, Toshio Sakakibara, Takayuki Sugisaka
-
Publication number: 20020005550Abstract: In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+-type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.Type: ApplicationFiled: April 6, 2001Publication date: January 17, 2002Inventors: Shigeki Takahashi, Hiroaki Himi, Satoshi Shiraki, Masatoshi Kato
-
Patent number: 6279585Abstract: In a method for manufacturing a semiconductor device, a barrier metal disposed on a metallic thin film for forming a thin film resistor is patterned by wet-etching. The wet-etching produces a residue of the barrier metal. The residue is removed after the oxidation thereof. Accordingly the residue is completely removed. As a result, the patterning of the thin film resistor is stably performed, and short-circuit does not occur to a wiring pattern disposed above the barrier metal.Type: GrantFiled: September 7, 1999Date of Patent: August 28, 2001Assignee: Denso CorporationInventors: Satoshi Shiraki, Makoto Ohkawa
-
Patent number: 6274452Abstract: After an insulating layer made of BPSG is formed on a diffusion layer, a contact hole is formed to expose the diffusion layer. Then, a first aluminum layer is formed in the contact hole. Then, first and second TEOS layers are formed. Thereafter, a thin film resistor is formed on the second TEOS layer by photo-lithography and etching treatments. In this process, the other parts are covered with the second TEOS layer to prevent being damaged. As a result, occurrence of a leak current at the diffusion layer and the like can be prevented. Further, a third TEOS layer is formed on the thin film resistor, and then a second aluminum layer is formed to be electrically connected to the thin film resistor through a contact hole by an ECR dry etching treatment. In this etching treatment, the thin film resistor is not damaged due to the third TEOS layer.Type: GrantFiled: November 5, 1997Date of Patent: August 14, 2001Assignee: Denso CorporationInventors: Shoji Miura, Satoshi Shiraki, Hajime Soga
-
Patent number: 6242792Abstract: A laser trimming is favorably performed by a strengthened laser beam energy. A level difference portion having a taper portion that is oblique with respect to the thicknesswise direction of a semiconductor substrate is formed at a surface of a semiconductor substrate. An insulating film is formed thereon and has its surface made flat, and then the thin film element is formed thereon. Thereafter, laser trimming is performed with respect to the thin film resistor. As a result, a state of interference between incident laser beam and reflected laser beam reflected from the interface between the semiconductor substrate and the insulating film is varied to thereby enable the production of a zone where laser beam energy is strengthened and a zone where laser beam energy is weakened.Type: GrantFiled: May 20, 1999Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Shoji Miura, Satoshi Shiraki, Tetsuaki Kamiya, Makio Iida