Patents by Inventor Satoshi Tanigawa

Satoshi Tanigawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6851599
    Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: February 8, 2005
    Assignee: Nitto Denko Corporation
    Inventors: Kei Nakamura, Satoshi Tanigawa, Shinya Oota
  • Patent number: 6772515
    Abstract: To provide a method of producing a multilayer printed wiring board that can be intended to have low-profile, light-weight and high-density wiring of a printed wiring board, and a multilayer printed wiring board produced by the method of producing a multilayer printed wiring board, the double-sided substrate is produced by the steps of forming an insulating resin layer on a metal foil; of forming a via hole in the insulating resin layer; of forming a first circuit pattern on the insulating resin layer and forming a conductive layer in the via hole, by plating; and of etching the metal foil to form it into a second circuit pattern. The produced double-sided substrate is used as a core substrate for producing multilayer printed wiring board by a laminate-en-bloc or a build-up method.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 10, 2004
    Assignees: Hitachi, Ltd., Nitto Denko Corporation
    Inventors: Tokihito Suwa, Atsushi Tanaka, Satoshi Tanigawa, Hirofumi Fujii, Kazunori Mune
  • Publication number: 20040035520
    Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.
    Type: Application
    Filed: March 5, 2003
    Publication date: February 26, 2004
    Inventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
  • Publication number: 20040011855
    Abstract: A method of producing a multilayer wired circuit board that can provide sufficient adhesion strength of the interface between a conductor layer and a thermosetting adhesive layer laminated, to provide improvement in connection strength between the conductor layers and thus improvement in reliability. In this method, after a thermosetting adhesive layer is formed on a first conductor layer, an opening is formed in the thermosetting adhesive layer and solder powders are charged in the opening at normal temperature. Sequentially, a second conductor layer is formed on the thermosetting adhesive layer including the opening filled with the solder powders. Thereafter, the solder powders are melted by heating, to electrically connect between the first conductor layer and the second conductor layer.
    Type: Application
    Filed: March 5, 2003
    Publication date: January 22, 2004
    Inventors: Kei Nakamura, Satoshi Tanigawa, Shinya Oota
  • Patent number: 6662442
    Abstract: A process for producing a printed wiring board, particularly an interposer for a chip size package, which comprises the steps of (1) forming an outer insulator layer 22 having outer via-holes 24 on a substrate 32, (2) forming conducting passages 31 through the outer via-holes 24 by plating with metal up to substantially the same level as the upper surface of the outer insulator layer 22, (3) forming a thin metal film 29 on the outer insulator layer 22 and on the conducting passages 31, (4) forming a conductor layer 21 in a prescribed circuit pattern on the thin metal film 29 by plating, (5) removing the part of the thin metal film 29 on which the conductor layer 21 is not formed, (6) forming an inner insulator layer 23 on the conductor layer 21, and (7) removing the substrate 32. The outer insulator layer is formed with flatness to secure good adhesion to a semiconductor chip.
    Type: Grant
    Filed: July 19, 2000
    Date of Patent: December 16, 2003
    Assignee: Nitto Denko Corporation
    Inventors: Kouji Matsui, Kazunori Mune, Hirofumi Fujii, Satoshi Tanigawa
  • Patent number: 6591491
    Abstract: A producing method of a multilayer circuit board for ensuring that a circuit board, such as an interposer, is provided on the multilayer circuit board. The method includes the steps forming the interposer on a support board; forming a multilayer circuit board separately from the interposer; joining the interposer formed on the support board to the multilayer circuit board; and then removing the support board. According to this method, even if the production of the interposer fails after the production of the multilayer circuit board, it is possible to scrap the interposer only and there is no need to scrap it together with the multilayer circuit board. Besides, although the interposer is thin and limp, since it is formed on the support board, the interposer can surely and readily be joined to the multilayer circuit board.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: July 15, 2003
    Assignee: Nitto Denko Corporation
    Inventors: Hirofumi Fujii, Satoshi Tanigawa
  • Publication number: 20020140076
    Abstract: First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 3, 2002
    Applicant: NITTO DENKO CORPORATION
    Inventors: Hiroshi Yamazaki, Mineyoshi Hasegawa, Satoshi Tanigawa
  • Publication number: 20020108781
    Abstract: A printed wiring board, particularly, an interposer 20 for a chip scale package, comprising an outer insulator layer 22 having outer electrodes 31, a conductor layer 21, and an inner insulator layer 23 having inner electrodes 27, the electrodes 31 and/or 27 having been formed by electroplating using, as a negative electrode, a metal plate 32 that has been provided on the outer insulator layer 22 and removed after the electroplating. Having no plating leads, the printed wiring board has the electrodes in an orderly array at a fine pitch and a high density.
    Type: Application
    Filed: April 11, 2002
    Publication date: August 15, 2002
    Applicant: NITTO DENKO CORPORATION
    Inventors: Kazunori Mune, Hirofumi Fujii, Satoshi Tanigawa
  • Publication number: 20020056192
    Abstract: To provide a method of producing a multilayer printed wiring board that can be intended to have low-profile, light-weight and high-density wiring of a printed wiring board, and a multilayer printed wiring board produced by the method of producing a multilayer printed wiring board, the double-sided substrate is produced by the steps of forming an insulating resin layer on a metal foil; of forming a via hole in the insulating resin layer; of forming a first circuit pattern on the insulating resin layer and forming a conductive layer in the via hole, by plating; and of etching the metal foil to form it into a second circuit pattern. The produced double-sided substrate is used as a core substrate for producing multilayer printed wiring board by a laminate-en-bloc or a build-up method.
    Type: Application
    Filed: September 25, 2001
    Publication date: May 16, 2002
    Inventors: Tokihito Suwa, Atsushi Tanaka, Satoshi Tanigawa, Hirofumi Fujii, Kazunori Mune
  • Patent number: 6379159
    Abstract: In a method for manufacturing an interposer for CSP and its intermediate body, a first insulating layer is formed on a cathode substrate. An opening is formed at a position in the insulating layer where a contact is to be formed so that the surface of the substrate is exposed to the inner bottom of the opening. The opening is filled with metal by the electroplating using the cathode substrate as a cathode to form a conductive path. A circuit pattern which is contact with the conductive path is formed on the insulating layer. The cathode substrate is removed partially or entirely so that the end surface of the conductive path is exposed to form a contact. This permits a variation of the heights of a plurality of contacts to be reduced.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: April 30, 2002
    Assignee: Nitto Denko Corporation
    Inventors: Kazunori Mune, Kazuo Ouchi, Satoshi Tanigawa, Hirofumi Fujii
  • Patent number: 6300037
    Abstract: An adhesive in the form of a patterned film is disclosed, which is obtained from a photositive resin composition and exhibits satisfactory adhesive properties even when used for electronic parts of various shapes having a rugged surface. The adhesive is obtained from a photosensitive polyimide resin precursor which, after pattern formation, melts upon heating. The adhesive has a melt viscosity at 250 ° C. from 1,000 to 1,000,000 Pa·s.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: October 9, 2001
    Assignee: Nitto Denko Corporation
    Inventors: Hirofumi Fujii, Satoshi Tanigawa
  • Publication number: 20010023532
    Abstract: A producing method of a multilayer circuit board for ensuring that a circuit board, such as an interposer, is provided on the multilayer circuit board. The method includes the steps of forming the interposer on a support board; forming a multilayer circuit board separately from the interposer; joining the interposer formed on the support board to the multilayer circuit board; and then removing the support board. According to this method, even if the production of the interposer fails after the production of the multilayer circuit board, it is possible to scrape the interposer only and there is no need to scrap it together with the multilayer circuit board. Besides, although the interposer is so thin and limp, since it is formed on the support board, the interposer can surely and readily be joined to the multilayer circuit board.
    Type: Application
    Filed: March 7, 2001
    Publication date: September 27, 2001
    Inventors: Hirofumi Fujii, Satoshi Tanigawa
  • Patent number: D436087
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: January 9, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Takami, Takashi Inoue, Satoshi Tanigawa
  • Patent number: D473853
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: April 29, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Inoue, Satoshi Tanigawa, Kiyoshi Kohno
  • Patent number: D476632
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: July 1, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Inoue, Satoshi Tanigawa, Kiyoshi Nakata
  • Patent number: D477292
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: July 15, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Inoue, Satoshi Tanigawa, Kiyoshi Nakata
  • Patent number: D482668
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: November 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Tanigawa, Takashi Inoue, Kiyoshi Kohno
  • Patent number: D487731
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: March 23, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Takami, Takashi Hasegawa, Satoshi Tanigawa
  • Patent number: D425050
    Type: Grant
    Filed: July 19, 1999
    Date of Patent: May 16, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoshi Tanigawa, Noriaki Mori, Takashi Inoue, Mitsuru Takami
  • Patent number: D434398
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: November 28, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuru Takami, Satoshi Tanigawa, Muneyuki Nagai